FinFET Gate Structure Mitigating CMP Recess Defects
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Solution Overview
Problem
Existing FinFET technologies face challenges in forming reliable gate structures with small critical dimensions, leading to issues in device performance and reliability as device sizes are reduced.
Innovation Solution
A method for forming a FinFET structure involves patterning fins using photolithography and self-aligned processes, forming a dummy gate structure, and using a conductive sealing layer to mitigate recess defects during chemical mechanical polishing, ensuring the gate structure's reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of FinFET device structure is reduced to achieve higher device density, then device density increases, but gate structure reliability deteriorates due to small critical dimension formation challenges
Solution Approach 1:
A dummy gate structure is formed before the actual gate structure to establish a reference plane and prevent recess defects during subsequent polishing processes. This preliminary structure ensures that when the real gate is formed, the underlying substrate is already protected from damage, maintaining gate structure reliability even as device dimensions are reduced for higher density.
Solution Approach 2:
The dummy gate structure acts as an intermediary element between the substrate and the actual gate formation process. It serves as a protective mediator that prevents direct damage to the substrate during CMP processes, thereby ensuring gate reliability while allowing continued scaling for higher device density.
2Ease of manufacture
If conventional photolithography and self-aligned processes are used to form fins, then manufacturing process simplicity is maintained, but recess defects occur during chemical mechanical polishing affecting gate structure reliability
Solution Approach 1:
The dummy gate structure is formed as a preliminary step before actual gate fabrication. This preliminary structure serves as a protective layer that prevents recess defects during CMP processes, thereby maintaining gate structure reliability without complicating the overall manufacturing flow.
Solution Approach 2:
The dummy gate acts as an intermediary protective layer during the CMP process. It mediates between the polishing contacts and the actual gate structure, preventing direct damage while allowing the use of conventional simple photolithography and self-aligned processes to continue.
3Quantity of substance
If device size is reduced to improve device density, then higher device density is achieved, but manufacturing precision deteriorates due to challenges in forming reliable gate structures with small critical dimensions
Solution Approach 1:
The dummy gate structure is formed in advance to establish a stable reference plane and protect the substrate before actual gate formation. This preliminary action ensures that even when critical dimensions are reduced for higher density, the gate formation process maintains precision because the underlying structure is already stabilized.
Solution Approach 2:
The dummy gate serves as an intermediary structure that maintains manufacturing precision during scaling. It provides a stable reference and protective layer that enables precise gate formation at smaller critical dimensions, thereby supporting higher device density without sacrificing manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the reliability of the gate structure and improves the yield of semiconductor devices by eliminating or mitigating recess defects, thereby ensuring consistent and reliable contact formation.
Implementation Method 1
successively removing the metal nucleation layer and the work function metal layer over the insulating layer by a first chemical mechanical polishing process
Implementation Method 2
patterning fins using photolithography and self-aligned processes
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure protruding therefrom, an insulating layer is over the substrate to cover the fin structure, a gate structure in the insulating layer and over the fin structure, and source and drain features covered by the insulating layer and over the fin structure on opposing sidewall surfaces of the gate structure. The gate structure includes a gate electrode layer, a conductive sealing layer covering the gate electrode layer, and a gate dielectric layer between the fin structure and the gate electrode layer and surrounding the gate electrode layer and the conductive sealing layer. The gate electrode layer has a material removal rate that is higher than the material removal rate of the conductive sealing layer in a chemical mechanical polishing process.