FinFET Gate Contact Isolation via Amorphous Silicon and Low-k Dielectric
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Solution Overview
Problem
Conventional finFET fabrication techniques often result in electrical shorts between gate contacts and epi S/D regions due to over etching, which affects the reliability and performance of integrated circuit devices.
Innovation Solution
A method is developed to form middle-of-line finFET devices by creating a non-trench silicide isolation structure, using an amorphous silicon layer, an oxide layer, and a low dielectric constant layer to prevent gate contact and epi S/D shorts, involving specific processing steps such as forming openings over the epi S/D regions and using materials like tantalum, tungsten, or aluminum for gate contacts, and silicon nitride caps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional trench silicide processing is used, then gate contact cavity formation is achieved, but over etching occurs that extends to epi S/D regions causing electrical shorts
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and depositing conformal dielectric layers (ILD1 and ILD2) before defining the final gate contact cavity. The mandrel serves as a sacrificial structure that pre-establishes the cavity boundaries, preventing over-etching into epi S/D regions. The conformal dielectric layers are deposited in advance to create isolation barriers before contact hole formation, ensuring precise etch stopping positions.
Solution Approach 2:
The patent uses an intermediary mandrel structure that mediates between the gate contact formation process and the epi S/D region protection requirement. The mandrel acts as a physical barrier and etch stop, preventing direct contact between the etching process and the epi S/D regions. Additionally, the conformal dielectric layers serve as intermediary isolation structures that prevent electrical shorts while allowing gate contact formation.
2Ease of manufacture
If replacement contact with low dielectric constant isolation techniques is used, then isolation is improved, but over etching creates cavities extending to epi S/D region causing shorts
Solution Approach 1:
The patent implements preliminary action by forming low dielectric constant isolation layers in the shallow trench isolation regions before gate contact cavity formation. This pre-established isolation structure prevents etch penetration into epi S/D regions during subsequent processing steps, eliminating the short circuit problem while maintaining ease of manufacture through standard STI process integration.
3Productivity
If critical dimensions are reduced for higher density, then device scaling is achieved, but conventional fabrication techniques reach their limitations
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar gate contact formation to a three-dimensional process using vertical mandrels and conformal dielectric layer deposition. This enables precise control of contact cavity dimensions through vertical layer thickness control rather than relying solely on lateral etch precision, allowing continued scaling at reduced critical dimensions.
Solution Approach 2:
The patent uses parameter changes by controlling the thickness and dielectric constant of conformal dielectric layers to precisely define etch stop positions. By adjusting layer thickness parameters and material properties, the process achieves high precision contact cavity formation at reduced dimensions, extending the scalability of fabrication techniques.
Data Source
AI summary
A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an α-Si layer in a recess over the epi S/D; forming an oxide layer over the α-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and α-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.