FinFET Gate Contact Etching with Selective Etch Stop Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in efficiently integrating high-density finFETs due to limitations in the formation of fin structures, gate dielectric layers, and contact formation processes, which affect the integration density and performance of semiconductor devices.
Innovation Solution
The method involves forming finFETs using a gate-last process, with specific steps including patterning fins, forming isolation regions, depositing dummy gate dielectric and electrode layers, replacing these with high-k gate dielectric and metal gates, and forming silicide regions and contacts, while utilizing selective etch stop layers to control etching processes and achieve vertical profiles for gate and source/drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional gate-first process is used, then manufacturing simplicity is maintained, but integration density and device performance are limited
Solution Approach 1:
The patent inverts the conventional gate-first process sequence by implementing a gate-last process where the gate electrode is formed after the source and drain regions. This inversion enables better control of vertical profiles and higher integration density by allowing the gate to be precisely positioned relative to the already-formed source/drain structures, thereby resolving the contradiction between productivity and device complexity.
Solution Approach 2:
The patent applies preliminary action by forming placeholder structures (such as mandrels or sacrificial layers) before the actual gate electrode formation. These preliminary structures guide the subsequent gate formation process, ensuring precise alignment and vertical profiles. This preliminary preparation enables the gate-last process to achieve high integration density without excessive process complexity.
2Productivity
If minimum feature size is reduced to increase integration density, then more components fit in given area, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes material parameters by using high-k gate dielectric materials with different dielectric constants and etch selectivities. These parameter changes enable precise control of gate thickness and profile at reduced feature sizes. The high-k materials allow for thinner effective gate lengths while maintaining electrical performance, thereby increasing integration density without proportionally increasing manufacturing precision requirements.
Solution Approach 2:
The patent introduces intermediary layers (such as spacer materials or etch stop layers) between the source/drain regions and the gate electrode. These intermediary structures act as self-aligned masks that automatically define the gate position and dimensions. This self-alignment mechanism reduces the need for high-precision lithography and alignment, enabling higher integration density with manageable manufacturing precision requirements.
3Reliability
If high-k gate dielectric and metal gates are used, then device performance is improved, but process complexity increases
Solution Approach 1:
The patent segments the gate structure into multiple functional layers: high-k dielectric layer, intermediate buffer layer, and metal gate electrode layer. Each layer is deposited and processed separately with optimized parameters. This segmentation allows each material to be tailored for its specific function (dielectric strength, adhesion, conductivity) while using standard deposition techniques, thereby achieving high device performance without excessive process complexity.
Solution Approach 2:
The patent designs the high-k gate dielectric structure to serve multiple functions: providing high dielectric strength for device performance, offering etch selectivity for self-aligned patterning, and enabling precise thickness control. This multi-functionality reduces the need for additional specialized process steps, allowing high device performance to be achieved with manageable process complexity.
Data Source
AI summary
Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first etch stop layer from a portion of a gate mask, the gate mask extending between spacers adjacent a gate electrode, the gate electrode overlying a semiconductor fin. The method further includes forming a second etch stop layer adjacent the first etch stop layer, forming an opening through the second etch stop layer, and exposing the first etch stop layer by performing a first etching process. The method further includes extending the opening through the first etch stop layer and exposing the gate electrode by performing a second etching process. Once the gate electrode has been exposed, the method further includes forming a gate contact in the opening.