FinFET Gate Contact Structure Isotropic Etching
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Solution Overview
Problem
FinFETs face high contact resistance due to small gate contact areas, which are limited by design rule constraints, hindering the increase in width and thus the drive current in integrated circuits.
Innovation Solution
The top portion of the gate in FinFETs is isotropically etched to expand the contact area between the gate contact and the gate without increasing the gate contact width, using a combination of wet and dry etching techniques to create a larger contact area within the gate electrode, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate contact width is increased to reduce contact resistance, then the contact resistance decreases, but the design rule limitations are violated
Solution Approach 1:
The patent transitions from a two-dimensional contact area (width × length) to a three-dimensional structure by forming an etched cavity in the gate electrode. The gate contact extends vertically into this cavity, creating additional contact surface area through the depth dimension. This dimensional transition allows the contact area to be increased without increasing the lateral width, thereby maintaining design rule compliance while reducing contact resistance.
Solution Approach 2:
The gate contact is nested within the etched cavity of the gate electrode, creating a nested structure where the contact is partially embedded in the gate. This nesting arrangement maximizes the contact area within the available lateral space, as the contact surface includes both the top surface and the sidewalls of the cavity, effectively increasing the contact area without increasing the overall footprint.
2Productivity
If the gate contact area is increased to reduce contact resistance, then the drive current increases, but the gate contact width cannot be increased due to design rule limitations
Solution Approach 1:
The patent utilizes the vertical dimension by etching a cavity into the gate electrode and extending the gate contact into this cavity. This creates additional contact area through the depth of the cavity rather than increasing the lateral width. The contact area is effectively multiplied by utilizing the third dimension (depth), allowing drive current to increase while maintaining compliance with width-based design rules.
Solution Approach 2:
The etched cavity in the gate electrode creates a porous or hollow structure that increases the internal surface area available for contact. By forming this cavity, the gate electrode provides additional contact surfaces (including sidewalls and bottom of the cavity) that increase the effective contact area without increasing the external dimensions, thereby enabling higher drive current while maintaining design rule compliance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance between the gate contact and the gate while adhering to design rule limitations, enhancing the drive current without violating any design rules, by increasing the contact area ratio between the expanded contact and the fin.
Implementation Method 1
using a combination of wet and dry etching techniques to create a larger contact area within the gate electrode
Implementation Method 2
using a combination of wet and dry etching techniques to create a larger contact area within the gate electrode
Data Source
AI summary
An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.