FinFET Gate Contact Structure With Intermediary Conductive Layer
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Solution Overview
Problem
Existing FinFET devices face challenges in reducing contact resistance between the gate electrode layer and the second conductive layer, particularly as the gate structure dimensions decrease, making it difficult to fill low-resistance materials and maintain performance.
Innovation Solution
A first conductive layer is formed between the gate electrode layer and the second conductive layer to reduce contact resistance, with the first conductive layer being selectively deposited over the gate electrode layer but not on the gate dielectric layer, and a barrier layer and second conductive layer are used to construct a gate contact structure, improving electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a direct contact structure is used between gate electrode layer and second conductive layer, then the device structure is simpler, but contact resistance increases and electrical connectivity deteriorates
Solution Approach 1:
A first conductive layer is introduced as an intermediary between the gate electrode layer and the second conductive layer. This intermediate layer improves electrical connectivity and reduces contact resistance by providing a transition interface that facilitates better charge transfer, while the overall structure remains manageable through systematic layering.
2Reliability
If low-resistance materials are used to fill the trench, then contact resistance decreases, but filling difficulty increases due to trench geometry and material constraints
Solution Approach 1:
The gate contact structure is segmented into multiple conductive layers (first conductive layer and second conductive layer) separated by a barrier layer. This segmentation allows each layer to be optimized independently for material properties and deposition processes, making it easier to fill the trench with low-resistance materials while maintaining control over the filling process.
Solution Approach 2:
The contact structure transitions from a single-layer approach to a multi-layer vertical structure. By adding the vertical dimension with multiple conductive layers and a barrier layer, the patent creates a more complex but manufacturable structure that addresses both the low-resistance requirement and the trench filling challenge through controlled deposition sequences.
3Productivity
If gate structure dimensions are reduced to increase device density, then device density increases, but contact resistance increases due to smaller contact area
Solution Approach 1:
The gate contact structure uses composite material layers including a first conductive layer, a barrier layer, and a second conductive layer. This composite structure allows optimization of each layer's material properties to maintain low contact resistance even as the overall gate dimensions are reduced for higher device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces contact resistance between the gate electrode layer and the second conductive layer, enhancing the performance of the FinFET device structure by allowing for better filling of the trench and reducing the native oxide layer on the gate electrode, thus improving overall device efficiency.
Implementation Method 1
a first conductive layer is formed over the gate electrode layer
Implementation Method 2
a first conductive layer is formed over the gate electrode layer
Data Source
AI summary
A method for forming a FinFET device structure is provided. The method includes forming a gate dielectric layer over a fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer. The method further includes forming a first dielectric layer formed over the gate dielectric layer. In addition, the method includes forming a first conductive layer on the gate dielectric layer. A bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer.