FinFET Gate Contact Layout for Misalignment and Leakage Control
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Solution Overview
Problem
In the fabrication of complementary metal-oxide-semiconductor (CMOS) integrated circuits, the shrinking technology nodes pose challenges such as misalignment of contacts leading to source/drain regions shorting with metal gate structures, exacerbated by decreasing gate length and spacing, which affects the performance and reliability of FinFET devices.
Innovation Solution
The implementation of a FinFET device with a metal gate electrode and high-dielectric-constant gate dielectric layers, which reduces gate leakage and maintains performance by allowing for a thicker physical thickness while maintaining effective thickness, and the use of a 'gate last' process to minimize subsequent high-temperature processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length and spacing between devices are decreased to improve device density, then productivity is improved, but manufacturing precision deteriorates due to misalignment of contacts with metal gate structures
Solution Approach 1:
The patent applies preliminary action by forming the metal gate structure before forming the source/drain contacts. This sequence allows the gate structure to serve as a reference for subsequent contact formation, improving alignment precision. The gate electrode is deposited and patterned first, then contacts are formed relative to this established structure, preventing misalignment issues that would occur if contacts were formed first.
Solution Approach 2:
The patent introduces an intermediary layer or process step between gate formation and contact formation. This intermediary step serves as a reference plane or alignment marker that facilitates precise contact placement relative to the gate structure, resolving the alignment precision problem that arises when decreasing gate length and spacing.
2Reliability
If high-dielectric-constant gate dielectric layers are used to reduce gate leakage, then reliability is improved, but device complexity increases due to additional processing steps
Solution Approach 1:
The patent merges the gate dielectric layer formation with the gate electrode formation into a single integrated process. The high-dielectric-constant material is deposited and patterned together with the metal gate electrode in one sequence, rather than as separate operations. This combining of steps reduces overall process complexity while maintaining the reliability benefits of the high-k dielectric layer.
Solution Approach 2:
The gate structure serves multiple functions: the high-dielectric-constant layer provides both electrical isolation and acts as part of the gate electrode structure itself. This multi-functionality eliminates the need for separate isolation layers, reducing processing steps while maintaining gate leakage reduction and reliability.
3Reliability
If a metal gate electrode is used instead of polysilicon to improve device performance, then reliability is improved, but ease of manufacture deteriorates due to additional processing requirements
Solution Approach 1:
The patent replaces the traditional polysilicon gate electrode with a metal gate electrode deposited using physical vapor deposition or similar techniques. This substitution enables better electrical performance and lower leakage while the deposition process integrates with existing fabrication workflows, managing the complexity of the manufacturing process.
Solution Approach 2:
The patent changes the material parameter of the gate electrode from polysilicon to metal, which fundamentally improves device performance and reliability. The processing requirements are managed by adjusting deposition parameters and integrating these steps into the existing fabrication sequence, balancing the improved performance with manageable manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the performance and reliability of FinFET devices by reducing gate leakage and improving alignment precision, thereby preventing short circuits and maintaining device efficiency with decreasing feature sizes.
Implementation Method 1
high-dielectric-constant (high-k) gate dielectric layers are also used which allow greater physical thicknesses while maintaining the same effective thickness
Data Source
AI summary
An IC structure includes a plurality of first fins, a plurality of second fins, a plurality of first gate structures, a plurality of second gate structures, and a first gate contact. The first fins and the second fins are over a substrate. The first gate structures traverse the plurality of first fins. The second gate structures traverse the plurality of second fins. The first gate structures have a first gate pitch. The second gate structures have a second gate pitch wider than the first gate pitch. The first gate contact is over a first one of the second gate structures. The first gate contact overlaps a location where the first one of the second gate structures traverses across a first one of the second fins.