FinFET Gate Structure Uniform Contact Plug Formation
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Solution Overview
Problem
The existing FinFET process faces challenges in achieving uniform contact plug formation due to uneven openings caused by the etching process for removing hard masks from gate structures, affecting device performance.
Innovation Solution
A semiconductor device design incorporating a substrate with a gate structure, spacer, contact etch stop layer, interlayer dielectric layer, and contact plug, where the contact plug is formed adjacent to one side of the gate structure, using a high-k last approach and replacement metal gate process to ensure even openings and improved contact plug formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etching process is used to remove hard mask from gate structure, then gate structure can be formed, but uneven openings are caused affecting contact plug formation
Solution Approach 1:
The patent segments the gate structure formation process into distinct steps: forming the gate electrode, then separately forming the contact holes. The contact holes are formed after the gate structure is complete, allowing independent optimization of each step. This segmentation eliminates the coupling between hard mask removal and contact hole formation that caused the uniformity issue.
Solution Approach 2:
The patent performs preliminary actions by forming the gate structure completely first (including gate electrode and associated layers), then uses this pre-formed structure as a template for subsequent contact hole formation. The contact holes are formed preliminarily planned around the gate structure, ensuring uniform openings that are not affected by the gate formation etching process.
2Reliability
If three-dimensional FinFET structure is used, then channel region control is improved, but process complexity increases
Solution Approach 1:
The patent applies local quality by forming the contact holes at specific locations relative to the gate structure (adjacent to gate edges, at defined distances). The contact hole formation process is localized to these specific regions, allowing the FinFET's three-dimensional channel control to be maintained while simplifying the overall process through targeted, location-specific contact formation rather than universal complex processing.
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; a spacer around the gate structure; a contact etch stop layer (CESL) on the spacer; an interlayer dielectric (ILD) layer adjacent to one side of the gate structure and contacting the CESL; and a contact plug adjacent to another side of the gate structure and contacting the CESL.