FinFET Gate Contact Structure With Sidewall Contact for Tighter CDs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area, requiring improved manufacturing processes to maintain efficiency and yield, particularly in forming gate contact structures for FinFET devices.
Innovation Solution
The process involves forming first trenches and fins on a substrate, filling them with dielectric material, recessing it to expose fin sidewalls, and creating a gate stack with multiple metal layers and a capping layer, followed by precise etching and planarization to form a gate contact with varying widths and shapes, allowing for reduced critical dimensions and improved manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and process control become more difficult
Solution Approach 1:
The gate contact structure is divided into multiple metal layers (first gate contact metal layer, second gate contact metal layer) with different widths. The lower metal layer has a wider bottom portion that provides a larger process window during formation, while the upper metal layer has a narrower width that achieves the desired small critical dimension. This segmentation allows each layer to be optimized independently for its specific function.
Solution Approach 2:
The patent transitions from a single-layer contact structure to a multi-layer vertical structure. By adding the vertical dimension with multiple metal layers at different depths, the design achieves small critical dimensions in the horizontal plane while maintaining manufacturability through the vertical stacking approach. The varying widths of different layers provide process tolerance in the vertical dimension.
2Manufacturing precision
If critical dimensions are reduced to improve device performance, then device functionality is enhanced, but process window becomes smaller and yield decreases
Solution Approach 1:
The gate contact is segmented into multiple metal layers where the lower layer has a wider bottom portion formed with a larger process window, while the upper layer has the narrower critical dimension. This segmentation allows the manufacturing process to achieve precise small dimensions in the upper layer while the lower layer provides tolerance buffering.
Solution Approach 2:
Different portions of the gate contact structure have different widths optimized for different functions. The bottom portion has a wider width for robust formation and electrical connection, while the top portion has a narrower width for achieving the required small critical dimension. Each local region is optimized for its specific requirement.
3Device complexity
If single-layer gate contact structure is used to simplify manufacturing, then process steps are reduced, but resistance increases and process window decreases
Solution Approach 1:
The gate contact is divided into multiple metal layers that can be formed using standard sequential deposition processes. The segmentation into layers with different widths allows optimization of both resistance and process window without requiring fundamentally new manufacturing techniques.
Solution Approach 2:
The patent combines multiple metal layers into a unified gate contact structure that functions as a single electrical pathway. The layers are merged vertically to provide both low resistance (through multiple parallel conduction paths) and a large process window (through the varying widths of different layers).
Data Source
AI summary
A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.