FinFET Replacement Gate Corners for Leakage and Short Prevention
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, challenges arise in reducing leakage current and improving yield due to the formation of conductive residues and shorts between epitaxial source/drain regions and the replacement gate stack, particularly in corner regions where the replacement gate stack is not formed.
Innovation Solution
The process involves forming a FinFET with a replacement gate stack that has rounded or chamfered edges by configuring the etching to leave remaining portions of the dummy gate stack in corner regions, which blocks the formation of the replacement gate stack, increasing the distance between the epitaxial source/drain regions and the gate stack, thereby reducing leakage current and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but leakage current increases and process yield decreases due to conductive residues and shorts
Solution Approach 1:
The patent applies curvature by forming rounded corners on the gate stack structure. Specifically, the gate stack is formed with rounded corners having a radius of curvature between 5-50 nm, which eliminates sharp corners where conductive residues tend to accumulate. This curvature modification prevents the formation of shorts between the gate stack and source/drain regions, thereby improving process yield while maintaining high integration density
2Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but leakage current increases due to conductive residues
Solution Approach 1:
The patent applies curvature by forming rounded corners on the gate stack structure. Specifically, the gate stack is formed with rounded corners having a radius of curvature between 5-50 nm, which eliminates sharp corners where conductive residues tend to accumulate. This curvature modification prevents the formation of shorts between the gate stack and source/drain regions, thereby improving process yield while maintaining high integration density
3Device complexity
If the dummy gate stack is completely removed to form the replacement gate stack, then the structure is simpler, but conductive residues cause shorts between epitaxial source/drain regions and the replacement gate stack
Solution Approach 1:
The patent applies local quality by selectively removing the dummy gate stack only from corner regions while leaving it intact in other areas. Specifically, the dummy gate stack is removed from corner regions to allow formation of the replacement gate stack, while portions of the dummy gate stack are retained in non-corner regions to prevent conductive residues from causing shorts. This localized approach maintains structural integrity while enabling successful gate replacement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current and the chance of shorts, enhances process window conditions, and improves yield by maintaining the distance between epitaxial source/drain regions and the replacement gate stack, leading to better device performance.
Implementation Method 1
performing an etching process on the dummy gate structure to form a recess in the dummy gate structure, wherein the etching process exposes the sidewall of the upper region
Data Source
AI summary
A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.