FinFET Gate Cut Last Scheme for Fin Formation
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Solution Overview
Problem
The existing gate cut processes for FinFET semiconductor devices are complex and time-consuming due to the need for separate multilayer patterning stacks and lithography processes, which can lead to erosion of spacers and dielectric layers, increasing the likelihood of contact-to-contact shorts.
Innovation Solution
A gate cut last scheme is implemented, where a placeholder gate structure with a sacrificial material is formed, and a first hard mask layer is deposited above it. A second mask layer is patterned to expose the first hard mask layer and sacrificial material, allowing for simultaneous removal and definition of a gate cut cavity, followed by filling with a dielectric material and subsequent replacement with conductive gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a separate multilayer patterning stack and lithography process is used for gate cut, then the gate structure can be defined, but the process complexity and fabrication time increase significantly
Solution Approach 1:
The patent combines the gate cut definition process with the existing fin cut process by using the same placeholder gate structure and etch process for both operations. The placeholder gate structure serves dual purposes: defining fin boundaries and defining gate cut locations, eliminating the need for a separate multilayer patterning stack and lithography process for gate cut.
Solution Approach 2:
The placeholder gate structure performs multiple functions: it acts as a sacrificial element during fin formation, defines the gate cut pattern, and serves as a template for the final gate structure. This multi-functional approach eliminates the need for separate process steps dedicated solely to gate cut definition.
2Manufacturing precision
If a separate multilayer patterning stack and lithography process is used for gate cut, then the gate structure can be defined, but the fabrication time increases
Solution Approach 1:
The patent merges the gate cut definition into the fin cut process flow, so that a single etch process simultaneously defines both fin boundaries and gate cut locations. This consolidation eliminates redundant lithography and patterning steps, directly reducing fabrication time while maintaining precise gate structure definition.
Solution Approach 2:
The placeholder gate structure is formed in advance during the fin formation process, before the actual gate structure is built. This preliminary action establishes the gate cut pattern early in the process flow, allowing subsequent steps to proceed without additional patterning operations and thus reducing overall fabrication time.
3Manufacturing precision
If conventional gate cut process is performed earlier in fabrication, then gate structure can be defined, but erosion of spacers and dielectric layers occurs increasing contact-to-contact shorts
Solution Approach 1:
The placeholder gate structure is formed preliminarily during fin formation, establishing the gate cut pattern before any erosion-prone processes occur. The actual gate cut is then performed using this pre-defined pattern, ensuring precise definition while avoiding the erosion issues that would occur if gate cut were performed later with additional patterning steps.
Solution Approach 2:
The placeholder gate structure acts as an intermediary element that defines the gate cut pattern without being the final gate structure itself. This intermediary structure allows the gate cut to be defined with high precision using the same material and process as the fins, while the actual gate structure is formed later with proper spacing, eliminating erosion-related reliability issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces erosion issues and simplifies the process flow, enhancing the precision and reliability of gate cut operations while minimizing the risk of contact-to-contact shorts.
Implementation Method 1
the etch process may erode the spacers 120
Data Source
AI summary
A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer is formed above the first hard mask layer. The second hard mask layer is patterned to define an opening therein exposing a portion of the first hard mask layer and being disposed above a portion of the placeholder gate structure. The exposed portion of the first hard mask layer and the portion of the sacrificial material of the placeholder gate structure disposed below the opening are removed to define a gate cut cavity and divide the placeholder gate structure into first and second segments. A dielectric material is formed in the gate cut cavity.