FinFET Gate Cut Layout for Logic Performance and Memory Density
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving optimal device performance and density in three-dimensional designs like FinFETs, particularly in balancing the parasitic capacitance of logic devices with the density of memory devices.
Innovation Solution
The formation of semiconductor structures involves creating distinct gate cutting structures with varying widths in logic and memory regions, using multi-patterning processes to enhance device performance in logic regions while improving density in memory regions, through the use of dummy and final gate stacks, spacer layers, and selective etching to form FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate cutting structures are formed with larger width in logic regions, then parasitic capacitance is reduced and device performance is improved, but device density is decreased
Solution Approach 1:
The patent applies different gate cutting structure widths to different functional regions: logic regions use larger width gate cutting structures to reduce parasitic capacitance and improve device performance, while memory regions use smaller width gate cutting structures to maximize device density. This spatial differentiation of structural parameters resolves the contradiction between performance and density by optimizing each region for its specific function.
2Reliability
If multi-patterning processes are used to create distinct gate cutting structures, then device performance and density are optimized, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into multiple patterning steps to create different gate cutting structure widths in different regions. This segmentation allows independent optimization of logic and memory regions, achieving the dual goal of high performance and high density despite the increased process complexity.
Solution Approach 2:
Different gate cutting structure configurations are applied to different functional regions (logic vs. memory) based on their specific performance requirements. This local differentiation enables simultaneous optimization of both device performance in logic regions and device density in memory regions.
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming first fin structures and a second fin structures over a substrate, forming a first gate stack and a second gate stack that extend in a first direction across the first fin structures and the second fin structures, respectively, and etching the first gate stack and the second gate stack to form a first trench through the first gate stack and a second trench through the second gate stack. A first dimension of the first trench in the first direction is greater than a second dimension of the second trench in the first direction. The method further includes forming a first gate cutting structure and a second gate cutting structure in the first trench and the second trench, respectively.