FinFET Gate Cut Method for Vertical Profile Precision
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Solution Overview
Problem
The challenge in manufacturing fin field effect transistors (FinFETs) lies in achieving critical dimension uniformity and forming non-tapered, vertical etch features through a taller dummy gate structure, particularly in the replacement metal gate (RMG) process, where precise definition of a sacrificial gate structure is crucial.
Innovation Solution
A gate cut scheme is implemented in the RMG process flow, where a sacrificial gate layer is formed over semiconductor fins, etched to create a gate cut opening between fins, followed by the deposition of a spacer layer and a fill layer, and then patterned using a hard mask to form sacrificial gate structures with precise, vertical profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a taller dummy gate structure is used to simplify etching and enable precise placement of vias or trenches, then ease of operation is improved, but manufacturing precision deteriorates due to difficulty in forming non-tapered vertical etch features with small critical dimension uniformity
Solution Approach 1:
The gate structure is segmented into multiple sections along its length, creating discrete gate segments separated by gaps. This segmentation allows each segment to be independently patterned and etched, enabling precise control over critical dimensions and vertical profiles while maintaining the benefits of a taller gate structure for via placement
Solution Approach 2:
The dummy gate structure is formed preliminarily before final gate patterning. This preliminary gate structure serves as a sacrificial element that defines the vertical profile and critical dimensions early in the process, allowing subsequent steps to build upon this precisely-defined foundation without exposing functional gate materials to activation thermal budgets
2Ease of manufacture
If the gate cut is performed after patterning the sacrificial gate, then the process follows conventional sequence, but it becomes difficult to achieve precise critical dimension definition and vertical profiles
Solution Approach 1:
The conventional sequence is inverted by performing the gate cut operation before patterning the sacrificial gate. This inversion allows the gate cut to define the critical dimensions and vertical profiles directly, while the subsequent sacrificial gate patterning fills in the remaining structure. This reverse sequence resolves the technical contradiction by achieving precise manufacturing requirements while maintaining process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the precise definition of sacrificial gate structures with small critical dimensions and vertical profiles, improving device density and performance by allowing for precise placement of vias and trenches, thereby simplifying the etching process and enhancing critical dimension uniformity.
Implementation Method 1
etching the sacrificial gate layer in a first etching step to form a gate cut opening that extends through the sacrificial gate layer
Implementation Method 2
forming a spacer layer on sidewalls of the gate cut opening
Implementation Method 3
depositing a fill layer within the gate cut opening to fill the gate cut opening
Data Source
AI summary
A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.