FinFET Gate Cut Plug Formation for Vertical Profile Control
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Solution Overview
Problem
Existing gate-cut processes for fin field effect transistors (FinFETs) face issues with poor profile control, non-selectivity, and undesirable gate height loss, particularly in cutting dummy gates and replacement metal gates, leading to epitaxial defects and vertical cut profile maintenance challenges.
Innovation Solution
A gate cut plug is formed using a dielectric material conformally on spacer sidewalls, followed by a planarizing material that completely fills gaps, ensuring a vertical profile and preventing gate etch damage by forming after dummy gate removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate cutting is performed in replacement metal gate hardmask, then gate length control is achieved, but final gate etch taper leads to epitaxial defects
Solution Approach 1:
The gate cut plug is formed preliminarily before the final gate etch step. By placing the dielectric plug material in the gate cut region prior to etching, the etch process is prevented from penetrating into the epitaxial region, thereby eliminating etch taper-induced defects while maintaining precise gate length control
Solution Approach 2:
A dielectric plug material serves as an intermediary element between the gate structure and the epitaxial region. This intermediary prevents direct contact between the etch process and the epitaxial layer, blocking the propagation of harmful etch taper effects while allowing precise gate patterning to occur
2Manufacturing precision
If dummy gate is cut, then gate contact prevention is achieved, but vertical cut profile control becomes difficult
Solution Approach 1:
The gate cut plug replicates the vertical profile of the surrounding gate structure by forming the dielectric material conformally on the spacer sidewalls. This copying approach ensures that the plug matches the vertical orientation of the gate, enabling precise gate contact prevention while maintaining excellent vertical cut profile control
3Adaptability or versatility
If selective etching is used for gate cutting, then material selectivity is improved, but gate height loss increases
Solution Approach 1:
The gate cut plug is formed preliminarily to define the gate cut region before any etching occurs. This preliminary placement of the dielectric plug prevents the etch process from removing gate material in the plug region, thereby eliminating gate height loss while maintaining material selectivity for differentiating gate cut regions from active gate regions
Data Source
AI summary
Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.