FinFET Gate Cut Region for NMOS PMOS Spacing
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in minimizing the distance between FinFET NMOS and PMOS transistors while avoiding process failures, which is crucial for improving productivity and transistor performance.
Innovation Solution
The method involves forming first and second fin-shaped active regions with different conductivity types in a semiconductor substrate, creating a gate cut region that overlaps the well boundary, and using a sacrificial gate and hardmask pattern to define gate trenches, allowing for the formation of gate electrodes with an interlayer insulating layer separating them, thereby reducing the distance between NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the distance between FinFET NMOS and PMOS transistors is reduced to improve integration density, then productivity and device performance are improved, but process failures occur due to manufacturing difficulties in limited space
Solution Approach 1:
The gate structure is segmented into separate gate electrodes for NMOS and PMOS transistors with a gate cut region between them. This segmentation allows independent formation and optimization of each gate electrode, reducing interference and process failures when transistors are closely spaced
Solution Approach 2:
An interlayer insulating layer is introduced as an intermediary between the gate electrodes of NMOS and PMOS transistors. This intermediate layer provides electrical isolation and structural support, enabling reduced transistor spacing without causing process failures related to gate interference or short circuits
2Productivity
If the distance between FinFET NMOS and PMOS transistors is reduced to improve integration density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The gate cut region and interlayer insulating layer are formed preliminarily before final gate electrode formation. This preliminary structuring establishes precise reference points and isolation boundaries that guide subsequent alignment steps, maintaining manufacturing precision even when transistors are closely spaced
Solution Approach 2:
The interlayer insulating layer serves as an intermediary reference structure that simplifies alignment procedures. By providing a stable, pre-formed layer between gate electrodes, it establishes clear alignment boundaries that reduce the complexity of precise positioning in high-density configurations
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.