FinFET Gate Line Cutting Area Optimization for Parasitic Capacitance
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Solution Overview
Problem
The design of semiconductor integrated circuits faces challenges in minimizing parasitic capacitance generated by conductive lines, particularly gate lines, due to changes in design rules, which requires an efficient method to optimize the layout without modifying existing design rules or applying additional Optical Proximity Correction (OPC) rules.
Innovation Solution
A method is introduced that involves pre-simulation and layout design of semiconductor integrated circuits with FinFET architecture, where a cutting area is modified by moving, extending, or duplicating to minimize overhead in conductive lines, using tools like the break, move, move-back, extension, and duplication tools, to satisfy design rules and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the cutting area is positioned according to standard design rules, then the layout satisfies manufacturing requirements, but the overhead of conductive lines increases causing higher parasitic capacitance
Solution Approach 1:
The patent applies local quality by differentiating the treatment of cutting areas based on their specific location and function. Different cutting areas are selectively moved, extended, or duplicated based on local requirements to minimize overhead in critical regions while maintaining standard design rule compliance in other areas. This localized optimization reduces parasitic capacitance without compromising overall manufacturing precision.
Solution Approach 2:
The patent implements preliminary action by proactively adjusting cutting area positions and dimensions during the design phase before fabrication. By pre-optimizing the cutting area layout to minimize conductive line overhead, the design prevents parasitic capacitance issues from arising in the first place, rather than attempting to correct them after manufacturing.
2Object-affected harmful factors
If additional OPC rules are applied to minimize overhead, then parasitic capacitance is reduced, but the design complexity and processing time increase
Solution Approach 1:
The patent applies self-service by enabling the design tool to automatically identify and optimize cutting areas that contribute to excessive overhead. The system autonomously selects which cutting areas to move, extend, or duplicate based on predefined criteria, eliminating the need for manual intervention or complex additional OPC rules. This self-optimizing approach reduces parasitic capacitance while keeping the design process simple and efficient.
3Object-affected harmful factors
If the cutting area is moved to minimize overhead, then parasitic capacitance is reduced, but the distance to device areas may violate design rules
Solution Approach 1:
The patent implements dynamics by making cutting area positions adjustable and adaptable rather than fixed. The system dynamically determines the optimal position for each cutting area by evaluating multiple factors including overhead minimization and design rule compliance. This dynamic positioning allows cutting areas to be moved to reduce parasitic capacitance while automatically ensuring minimum distance requirements to device areas are maintained.
Solution Approach 2:
The patent applies asymmetry by allowing different cutting areas to have different positions, dimensions, and adjustment strategies based on their specific context. Rather than applying a uniform rule to all cutting areas, the system asymmetrically optimizes each cutting area individually, moving or extending them differently according to local requirements. This asymmetric approach enables parasitic capacitance reduction while maintaining design rule compliance in each specific location.
Data Source
AI summary
A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.