FinFET Metal Gate Cutting Without Residue or CD Loss
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Solution Overview
Problem
Conventional metal gate cutting techniques for FinFETs struggle to remove metal residue at smaller technology nodes, leading to isolation issues and changes in critical dimensions due to horizontal etching, which complicates the fabrication of advanced integrated circuits.
Innovation Solution
The method involves creating a cut window in an overlaying patterning layer to expose metal gate structures and inter-layer dielectric layers, using anisotropic etching with multiple cycles and an etch protection layer to remove the exposed materials without horizontal expansion, ensuring residue-free cutting and maintaining critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional metal gate cutting techniques are used, then metal residue is removed, but horizontal expansion of cut windows occurs and critical dimensions change
Solution Approach 1:
The patent segments the metal gate cutting process into multiple controlled etching cycles separated by spacer deposition steps. Each cycle removes a portion of the metal gate while spacers prevent lateral etching, dividing the single-step problematic process into manageable stages that maintain precision while ensuring complete removal.
Solution Approach 2:
The patent applies preliminary action by depositing spacer layers before each etching cycle. These spacers are formed in advance to define precise boundaries that prevent horizontal expansion during etching, ensuring critical dimensions are maintained before the actual metal removal occurs.
2Reliability
If etching is performed to remove metal residue, then isolation issues occur, but complete removal is not achieved
Solution Approach 1:
The patent introduces spacer layers as intermediary materials between the etching process and the metal gate. These spacers act as protective mediators that allow complete metal removal while preventing lateral etching that would cause isolation issues, enabling both complete removal and dimension stability.
Solution Approach 2:
The patent employs periodic action through multiple alternating cycles of spacer deposition and etching. This periodic process allows systematic removal of metal gate material in controlled increments, ensuring complete removal while maintaining cut window dimensions through the protective spacer layers formed in each cycle.
3Manufacturing precision
If multiple etching cycles are used with spacers, then residue-free cutting is achieved, but process complexity increases
Solution Approach 1:
The patent applies self-service through self-aligned spacer deposition where the spacer material automatically conforms to the metal gate structure. This self-alignment mechanism eliminates the need for separate alignment steps, reducing process complexity despite multiple cycles, as each spacer automatically positions itself relative to the metal gate without additional lithography or alignment operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively removes metal residue without expanding the cut window, improving FinFET device operation by preventing isolation issues and maintaining precise dimensions, thus enhancing the fabrication of advanced integrated circuits.
Implementation Method 1
removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer between and adjacent to the first and second gate structures
Implementation Method 2
using etch protection layers to prevent horizontal expansion
Data Source
AI summary
Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.