FinFET Gate Dielectric Bar for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional scaled-down FinFETs suffer from excessive gate-to-contact parasitic capacitance, which increases the effective capacitance of integrated circuits and degrades chip performance.
Innovation Solution
Incorporating a dielectric bar within the gate area of FinFET structures, which reduces gate-to-contact parasitic capacitance by creating a dielectric spacer on each sidewall of semiconductor fins, forming a dielectric bar between these spacers, and then removing the spacers to allow for a metal gate formation over the dielectric bar, thereby reducing the effective capacitance of the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET devices are scaled down to continue CMOS technology scaling, then electrostatic control and current-voltage characteristics are improved, but gate-to-contact parasitic capacitance increases and dominates total device capacitance
Solution Approach 1:
The gate region is segmented by introducing a dielectric bar that divides the gate into separate sections. This segmentation electrically isolates different portions of the gate, reducing the parasitic capacitance between gate and contact regions while maintaining the beneficial electrostatic control of the scaled FinFET structure.
Solution Approach 2:
A dielectric bar is introduced as an intermediary element within the gate region. This dielectric material acts as an electrical insulator that reduces parasitic capacitance coupling between gate electrodes and contact regions, thereby reducing the harmful capacitive effects while preserving device performance.
2Productivity
If FinFET devices are scaled down, then device density and integration are improved, but parasitic capacitance increases and degrades chip performance
Solution Approach 1:
By segmenting the gate structure with a dielectric bar, the patent reduces parasitic capacitance in high-density FinFET arrays. This allows continued scaling and increased device density while mitigating the parasitic capacitance that would otherwise degrade performance in densely integrated circuits.
Solution Approach 2:
The patent modifies the electrical parameters of the gate region by introducing dielectric material with specific permittivity characteristics. This parameter change reduces the effective capacitance in the gate-to-contact path, enabling high-density integration without performance degradation from parasitic effects.
3Object-generated harmful factors
If a dielectric bar is added within the gate area, then effective capacitance is reduced, but device structure and manufacturing process become more complex
Solution Approach 1:
The dielectric bar formation process is merged with existing gate fabrication steps. The dielectric material is deposited and patterned in conjunction with gate electrode formation, combining multiple functions into a unified process flow that reduces overall manufacturing complexity despite the additional structural element.
Solution Approach 2:
The dielectric bar serves multiple functions simultaneously: it reduces parasitic capacitance, provides electrical isolation, and can serve as a spacer or alignment reference for subsequent processing steps. This multi-functionality justifies the additional structural element by delivering multiple benefits from a single feature.
Data Source
AI summary
A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.