FinFET Gate Structure with Dielectric Block for Parasitic Capacitance Reduction
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Solution Overview
Problem
FinFET devices experience increased parasitic capacitance due to scaling, which degrades device performance and slows down speed, necessitating a reduction in parasitic capacitance for 14 nm technology nodes and below.
Innovation Solution
A dielectric block is formed between the sidewalls of a gate structure, separating first and second fins on a substrate, with a gate electrode covering the dielectric block, reducing the effective area of conductive materials parallel to source drain contacts and thereby minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET devices are scaled down to 14 nm node and below, then device density and integration are improved, but parasitic capacitance increases and device speed degrades
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate electrode and second gate electrode) that can be independently controlled. This segmentation allows for optimized voltage control over different regions of the channel, improving carrier mobility and reducing parasitic capacitance effects at scaled dimensions while maintaining high device density
Solution Approach 2:
A dielectric material is introduced as an intermediary between the gate electrodes and the channel region. This dielectric layer reduces direct parasitic capacitance between the gate and source/drain contacts while maintaining electrical control over the channel, thereby improving device speed at scaled nodes
2Productivity
If gate pitch is scaled down to increase device density, then integration is improved, but parasitic gate to source and drain contact capacitance increases
Solution Approach 1:
Different regions of the gate structure are assigned different electrical potentials and control characteristics. The first and second gate electrodes can be independently biased to optimize carrier control in different channel regions, reducing parasitic capacitance effects locally while maintaining overall high device density through compact pitch scaling
Data Source
AI summary
A semiconductor device comprising a substrate, a first fin and a second fin disposed on the substrate and an isolation material disposed on the substrate, wherein the isolation material separates the first fin and the second fin. A dielectric block is disposed between the first fin and the second fin, wherein the dielectric block is over the isolation material. A gate electrode covers the dielectric block.