FinFET Gate Dielectric Oxidation Deposition Layering
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Solution Overview
Problem
In highly integrated semiconductor devices, forming a reliable gate dielectric structure in FinFET devices with reduced size is challenging due to difficulties in achieving consistent and effective dielectric layers.
Innovation Solution
A semiconductor device with a gate dielectric structure comprising an oxidation oxide layer and a deposition oxide layer, where the deposition oxide layer is interposed between the gate electrode and the fin active region, and the oxidation oxide layer is interposed between the deposition oxide layer and the fin active region, with the oxidation oxide layer being thicker than the deposition oxide layer, and having a high-k dielectric constant to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of FinFET devices is reduced to achieve higher integration, then device density increases, but forming a reliable gate dielectric structure becomes difficult
Solution Approach 1:
The gate dielectric structure is segmented into multiple distinct layers: a first gate dielectric layer (silicon oxide) and a second gate dielectric layer (high-k dielectric material). This segmentation allows each layer to perform its specific function - the first layer provides a high-quality interface with the semiconductor substrate, while the second layer provides high breakdown voltage and gate control, collectively solving the reliability issue in scaled devices
Solution Approach 2:
The gate dielectric structure uses composite materials by combining silicon oxide (first gate dielectric layer) with high-k dielectric materials (second gate dielectric layer such as hafnium oxide, aluminum oxide, or lanthanum oxide). This composite structure leverages the complementary properties of each material to achieve both good interface characteristics and high gate control in reduced-size FinFET devices
2Device complexity
If a single-layer gate dielectric is used to simplify structure, then device complexity decreases, but dielectric reliability and gate control deteriorate
Solution Approach 1:
The gate dielectric is divided into functionally distinct segments: the first layer (silicon oxide) formed by thermal oxidation provides a high-quality interface, and the second layer (high-k dielectric) deposited by ALD or PECVD provides high breakdown voltage. This segmentation achieves superior reliability without requiring complex multi-material interfaces
Solution Approach 2:
The first gate dielectric layer (silicon oxide) is formed by thermal oxidation before depositing the second gate dielectric layer. This preliminary action creates a high-quality interface foundation that ensures excellent electrical characteristics and reliable operation for the subsequent high-k dielectric layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution improves the reliability of the gate dielectric structure by ensuring a thicker oxidation oxide layer that is not extended to the lateral surface of the gate electrode, thereby maintaining the integrity and performance of the FinFET device.
Implementation Method 1
an oxidation oxide layer and a deposition oxide layer
Implementation Method 2
a deposition oxide layer formed of a high-k dielectric
Data Source
AI summary
A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.