FinFET Gate Dielectric Thickness Variation for Inter-Fin Spacing
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Solution Overview
Problem
In integrated circuit manufacturing, the use of different thickness insulators for fin-type field effect transistors (FINFETs) often results in suboptimal inter-fin spacing, leading to manufacturing challenges and compromised device performance, as thicker insulators can cause gaps between fins to be too small for effective device formation.
Innovation Solution
A method is developed to pattern a substrate with laterally adjacent fins, forming an isolation layer and a sacrificial gate, oxidizing and thinning the fins to create a uniform thickness work function metal layer, and using multiple insulator layers to maintain sufficient spacing between fins, allowing for the formation of gate conductors and source/drain structures without compromising inter-fin spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thicker insulators are used for fin-type field effect transistors, then device performance is improved, but inter-fin spacing becomes too small for effective device formation
Solution Approach 1:
The patent applies local quality by forming different thickness insulator layers on different fins within the same integrated circuit device. Specifically, first insulator layers with a first thickness are formed on first fins, while second insulator layers with a second thickness (different from the first) are formed on second fins. This allows each fin to have optimized insulator thickness tailored to its specific device performance requirements, while maintaining adequate inter-fin spacing for effective device formation.
2Reliability
If different thickness insulators are used for different fins, then device performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent implements segmentation by dividing the insulator formation process into distinct stages. First insulator layers are formed on first fins, then second insulator layers are formed on second fins with different thickness characteristics. This segmented approach allows independent optimization of insulator thickness for different fin types while maintaining a systematic manufacturing process that can be integrated into existing fabrication workflows.
Solution Approach 2:
The patent applies preliminary action by forming the first insulator layers on the first fins before forming the second insulator layers on the second fins. This sequential preparation allows subsequent processing steps to be optimized for each fin type independently, reducing overall manufacturing complexity compared to forming all insulators simultaneously with uniform thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent and effective formation of gate conductors and source/drain structures by maintaining sufficient gaps between fins, even with different thickness insulators and fin widths, thereby improving device performance and manufacturing efficiency.
Implementation Method 1
the first fins are oxidized to form a first oxide on the first fins and to thin (reduce the width of) the first fins
Data Source
AI summary
First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.