FinFET Gate Dielectric Thickness Variation for GIDL Reduction
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Solution Overview
Problem
FinFET electronic components, such as input/output (I/O) components, suffer from significant gated-induce drain leakage (GIDL) due to dense electric field lines at the top portion of the fin, which affects their reliability.
Innovation Solution
The semiconductor device incorporates a gate dielectric layer with varying thickness regions, including a thicker region abutting the drain and a thinner intermediate region, reducing the vertical electric-field strength and GIDL. This is achieved through an oxidization process that forms multiple oxide layers with different thicknesses, and a method involving pseudo gate structures, epitaxial growth of source and drain regions, and the deposition of high-K dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FinFET structure is used to improve gate control capabilities, then the short channel effect is reduced, but the gated-induce drain leakage becomes relatively large
Solution Approach 1:
The gate dielectric layer is designed with non-uniform thickness, where the first region adjacent to the drain has a greater thickness than the third region in the middle. This local variation in dielectric thickness creates a corresponding variation in electric field distribution, reducing the peak electric field strength at the drain-gate overlap region where GIDL occurs, while maintaining effective gate control in other regions.
Solution Approach 2:
The invention changes the physical parameter of gate dielectric thickness from a uniform value to a spatially varying value. By increasing the thickness in specific regions (particularly near the drain), the electric field strength is reduced in those areas, thereby suppressing GIDL without compromising the overall gate control capability of the FinFET structure.
2Object-generated harmful factors
If the gate dielectric layer thickness is increased to reduce GIDL, then the vertical electric-field strength is reduced, but the gate control capability may be affected
Solution Approach 1:
Rather than uniformly increasing the gate dielectric thickness which would compromise gate control, the invention applies increased thickness locally only in the first region adjacent to the drain where GIDL occurs. The third region in the middle maintains a smaller thickness to preserve strong gate control. This selective local thickening resolves the contradiction by targeting only the problematic area.
Solution Approach 2:
The gate dielectric layer is segmented into multiple regions with different thickness characteristics: a first region with greater thickness near the drain to reduce GIDL, a third region with smaller thickness in the middle for strong gate control, and potentially a second region connecting them. This segmentation allows each region to be optimized for its specific function without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases GIDL by increasing the thickness of the gate dielectric layer between overlapping portions of the drain and gate, thereby reducing the vertical electric-field strength and enhancing the reliability of FinFET electronic components.
Implementation Method 1
performing an oxidization process, so as to oxidize the first fin below edges of the first dielectric layer and the first pseudo gate structure, thereby forming a first portion of a first oxide layer
Implementation Method 2
performing an epitaxial process, so as to epitaxially grow a semiconductor material in the first recess and the second recess, thereby forming a first source region and a first drain region
Data Source
AI summary
This disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device may include a substrate; a first fin on the substrate for forming a first electronic component; a first gate structure on a portion of the first fin including a first gate dielectric layer on a portion of the first fin and a first gate on the first gate dielectric layer; and a first source region and a first drain region that each at one of two sides of the first gate structure and at least partially located in the first fin, where the first gate dielectric layer comprises a first region abutting against the first drain region, a second region abutting against the first source region, and a third region between the first region and the second region, and wherein thickness of the first region is greater than that of the third region.