FinFET Gate Electrode Miniaturization via Protective Film

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge in semiconductor manufacturing is the difficulty in finely manufacturing the gate electrode of multi-gate structure field-effect transistors due to the concave-convex surface, which affects the electrostatic control and current management.

Innovation Solution

A field-effect transistor design with a gate electrode that has a convex portion partially in contact with at least two faces of the fin region, allowing for further miniaturization and improved electrostatic control, along with a manufacturing method involving the formation of a semiconductor layer with a fin region, source, and drain regions, and a gate electrode that contacts the fin region through an etching selection ratio film.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a multi-gate structure with fin region is used to enhance electrostatic control, then current control capability is improved, but manufacturing precision of gate electrode deteriorates due to concave-convex surface

Engineering Contradiction:
Improveelectrostatic control capabilityVSAvoidgate electrode manufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

A protective film is formed on the fin region before gate electrode formation. This preliminary protective layer enables precise gate electrode patterning on the concave-convex surface by providing a planar working surface, while the gate electrode is formed with convex portions that make contact with multiple faces of the fin region through this film, thus maintaining both manufacturing precision and electrostatic control capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protective film acts as an intermediary layer between the fin region and the gate electrode. It mediates the interaction by providing a planar surface for precise gate electrode formation while still allowing the gate electrode's convex portions to contact multiple faces of the fin region through the film, thereby resolving the contradiction between manufacturing precision and electrostatic control

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of moving object

If gate electrode is miniaturized to improve device integration, then device density is improved, but manufacturing difficulty increases due to concave-convex surface

Engineering Contradiction:
Improvegate electrode areaVSAvoidgate electrode fabrication ease
Core Design Contradiction:
Area of moving objectVSEase of manufacture

Solution Approach 1:

The protective film is formed preliminarily on the fin region before gate electrode miniaturization. This preliminary protective layer provides a planar surface that facilitates precise miniaturization of the gate electrode, enabling smaller gate electrode areas to be fabricated with high precision on the concave-convex fin structure

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protective film introduces an additional dimensional layer between the fin region and gate electrode. This extra dimension provides a planar working surface that enables precise miniaturization of the gate electrode, allowing the gate electrode to be formed at reduced dimensions while maintaining manufacturing precision through the intermediate film layer

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8604528B2Field-effect transistor, field-effect transistor manufacturing method, solid-state imaging device, and electronic apparatus
Publication Date: 2013.12.10 SONY GROUP CORP
  • US8604528B2 patent drawing
  • US8604528B2 patent drawing
  • US8604528B2 patent drawing

AI summary

According to the present disclosure, it is possible to further miniaturize the gate electrode of the field-effect transistor. The field-effect transistor includes a substrate; a semiconductor layer configured to be formed on the substrate and have a fin region formed thereon with a source region and a drain region formed at both ends of the fin region; and a gate electrode configured to have a convex portion partially in contact with at least two faces of the fin region.