FinFET Gate-End Structure for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As critical dimensions of transistors continue to shrink, there is a need to reduce parasitic capacitance between various components in three-dimensional transistor structures, such as gate-all-around (GAA) and fin field-effect transistors (FinFETs), to enhance integration density and performance in integrated circuits.
Innovation Solution
The device structure incorporates nanosheet gate-all-around field-effect transistors with gate electrodes having a shorter gate-end portion located on shallow trench isolation (STI), which reduces parasitic capacitance by minimizing the length of the gate-end portions and using dielectric units with specific configurations to connect to the gate structures and STI, thereby minimizing capacitance between adjacent layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate-end portion length is increased to simplify manufacturing, then the ease of manufacture is improved, but the parasitic capacitance increases
Solution Approach 1:
The patent changes the critical dimension parameter of the gate-end portion to a specific range (3 nm to 20 nm) to optimize the balance between manufacturability and parasitic capacitance reduction. This parameter optimization allows the structure to be manufactured with current lithography tools while achieving significant parasitic capacitance reduction.
Solution Approach 2:
The patent applies different structural treatments to different regions: the gate-end portion has a controlled length of 3-20 nm to minimize capacitance, while the main gate structure maintains standard dimensions for functionality. This localized optimization reduces parasitic capacitance without compromising overall device performance.
2Productivity
If the integration density is increased by shrinking transistor dimensions, then the productivity is improved, but the parasitic capacitance between adjacent components increases
Solution Approach 1:
The patent transitions from planar gate structures to gate-all-around three-dimensional structures, wrapping the gate electrode around the channel in multiple dimensions. This 3D configuration reduces the lateral overlap between adjacent transistors, thereby reducing parasitic capacitance while enabling higher integration density.
Solution Approach 2:
The patent segments the gate structure into distinct components: the main gate portion and the gate-end portion. By separating these functions and optimizing the gate-end portion length to 3-20 nm, the structure achieves better electrical isolation between adjacent devices, reducing parasitic capacitance effects.
3Object-generated harmful factors
If the gate-end portion length is reduced to minimize parasitic capacitance, then the parasitic capacitance is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent specifies a gate-end portion length range of 3 nm to 20 nm that balances parasitic capacitance reduction with manufacturability. This parameter window is wide enough to accommodate variations in current lithography processes while still achieving significant capacitance reduction, making the design robust to manufacturing tolerances.
Data Source
AI summary
A device structure includes a substrate, a fin structure disposed on the substrate and elongated in an X direction, a gate structure formed on the fin structure and elongated in a Y direction transverse to the X direction to terminate at two opposite ends, at least one dielectric portion connected to at least one of the two opposite ends of the gate structure, and having two sides that are opposite to each other in the X direction, and a pair of gate spacers which are spaced apart from each other in the X direction and are respectively disposed on two lateral sides of the gate structure, and which are elongated in the Y direction to cover the two sides of the dielectric portion, respectively. A method for manufacturing the device structure is also disclosed.