FinFET Gate Work Function Layering to Prevent Etch Penetration
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing FinFET devices due to complexities arising from the scaling down process, particularly in forming fins and isolation structures with precise dimensions and depths, which affects the integration of transistors with different threshold voltages and prevents undesired etching penetration.
Innovation Solution
A method involving the formation of trenches, dielectric filling, and recessing to create semiconductor fins and isolation structures, followed by the deposition and etching of work function metal layers with varying thicknesses and BARC layers to prevent etchant flow and achieve distinct threshold voltages in transistors, is employed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the scaling down process is used to increase functional density, then production efficiency is improved and costs are lowered, but the complexity of processing and manufacturing increases
Solution Approach 1:
The patent segments the transistor fabrication process into distinct stages: forming isolation structures in trenches, creating fins through selective epitaxial growth, and depositing gate structures. This segmentation allows each step to be optimized independently, managing the complexity introduced by scaling while maintaining high functional density
Solution Approach 2:
The patent applies local quality by creating different threshold voltages in adjacent transistors through selective doping of isolation structures. The isolation structures have different dopant concentrations compared to the substrate, enabling local customization of transistor characteristics without affecting the entire wafer, thus managing processing complexity while achieving high functional density
2Manufacturing precision
If fins and isolation structures are formed with precise dimensions and depths, then transistor integration with different threshold voltages is enabled, but etching penetration control becomes more difficult
Solution Approach 1:
The patent performs preliminary action by forming a protective dielectric layer over the isolation structures before etching the gate trench. This pre-formed protective layer prevents etchant penetration into the isolation structures, ensuring precise dimensional control of fins and isolation structures while simplifying the etching process by eliminating the need for complex etching parameter control
Solution Approach 2:
The protective dielectric layer acts as an intermediary between the etchant and the isolation structures. It mediates the etching process by allowing the etchant to remove the dummy gate material while preventing penetration into the isolation structures, thus achieving precise dimensional control without complex etching penetration control
3Adaptability or versatility
If work function metal layers with varying thicknesses are deposited, then transistors with distinct threshold voltages are achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies local quality by depositing work function metal layers with spatially varying thicknesses over different transistor regions. The deposition process creates thicker metal layers over first transistors and thinner layers over second transistors, enabling local customization of threshold voltages. This approach achieves adaptability in threshold voltage differentiation while keeping the manufacturing process relatively simple by using a single deposition step with appropriate masking or controlled deposition parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the integration of transistors with different threshold voltages while preventing etching penetration, enhancing manufacturing efficiency and device performance.
Implementation Method 1
etching a dummy gate to form a gate trench in a dielectric structure
Implementation Method 2
depositing a gate dielectric layer over the channel portion of the first semiconductive fin and the first isolation structure; depositing a first work function layer over the gate dielectric layer
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes etching a dummy gate to form a gate trench to expose a channel portion of a first fin and a first isolation structure; depositing a gate dielectric layer and first and second work function layers, wherein the second work function layer has a first portion directly over the channel portion of the first fin and a second portion directly over the first isolation structure; etching the second portion of the second work function layer, wherein the first portion of the second work function layer remains; depositing a third work function layer over and in contact with the first portion of the second work function layer and the first work function layer; and filling the gate trench with a gate metal.