FinFET Gate Etching with Offset RF Timing for Fin Loss Control
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling the profile and volume of epitaxial source/drain regions in FinFET devices due to limitations in fin loss management during gate structure formation, particularly as feature sizes shrink and spacing between gates becomes narrower.
Innovation Solution
The method involves a multi-step plasma etching process with controlled radio frequency (RF) power sources, where the top RF power source is alternately turned on and off, and the bottom RF power source is also alternately turned on and off with a timing offset, allowing for precise adjustment of the gate layer patterning and fin loss to achieve targeted sidewall profiles and recess sizes for epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-step plasma etching is used for gate layer patterning, then the process is simple and fast, but the control over fin loss and sidewall profile is insufficient
Solution Approach 1:
The patent divides the single plasma etching process into multiple sequential etching steps, each with distinct RF power configurations. The top RF power source and bottom RF power source are independently controlled with different duty cycles, allowing separate optimization of sidewall profile formation and fin loss control in each step.
Solution Approach 2:
The patent dynamically adjusts the duty cycles of top and bottom RF power sources during the etching process. By varying the duty cycle ratios between different etching steps, the process adapts to achieve different sidewall profiles and fin loss characteristics, transforming a static single-step process into a dynamic multi-parameter control system.
2Area of moving object
If feature sizes are reduced to increase integration density, then more components fit in given area, but control over epitaxial source/drain region profile becomes more difficult
Solution Approach 1:
The patent applies different RF power duty cycles to different spatial zones of the etching process. The top RF power source controls sidewall profile formation while the bottom RF power source controls fin loss, allowing localized quality control in different regions of the fin structure even as overall dimensions shrink.
Solution Approach 2:
The patent changes multiple process parameters simultaneously - top RF power duty cycle, bottom RF power duty cycle, and etching step sequencing - to maintain control over epitaxial source/drain region profiles. This multi-parameter adjustment compensates for the reduced margin for error in smaller feature sizes.
3Manufacturing precision
If additional processing steps are added to control epitaxial source/drain region size and shape, then manufacturing precision improves, but productivity decreases
Solution Approach 1:
The patent merges multiple control functions into a single integrated plasma etching process. By combining sidewall profile control and fin loss control into one multi-step etching sequence with coordinated RF power sources, it achieves the precision of multiple separate processes without requiring additional discrete processing steps.
Solution Approach 2:
The patent makes the plasma etching tool multi-functional by enabling it to perform both sidewall profile formation and fin loss control through independent RF power source control. This universal approach allows one process step to accomplish what would traditionally require multiple specialized steps, maintaining productivity while improving precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides additional control over the size and shape of epitaxial source/drain regions, enhancing the precision and flexibility in semiconductor manufacturing, even in tight spaces, without requiring additional processing steps.
Implementation Method 1
patterning the gate layer comprises turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process
Data Source
AI summary
A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.