FinFET Gate Extension Layout for Hot Carrier Reliability
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Solution Overview
Problem
Highly-scaled FinFETs incorporating laterally-diffused drain implants are susceptible to premature failure and performance degradation due to hot carrier effects, such as impact ionization damaging thin gate insulators, which reduces reliability and increases leakage.
Innovation Solution
Incorporating a gate extension structure into LDMOS FinFETs, where the gate extension is electrically coupled to the semiconductive fin and disposed above the field insulator material within a gap region, mitigates performance degradation by influencing electric field distribution and carrier concentration, and can be fabricated using existing semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If device dimensions are reduced to increase switching speeds, then switching speed is improved, but susceptibility to leakage and breakdown increases
Solution Approach 1:
The patent transitions from planar MOSFET architecture to three-dimensional FinFET architecture with vertical fins extending from the substrate. This dimensional change allows the gate to control current flow from multiple directions (top and sidewalls), providing superior electrostatic control in highly-scaled devices and reducing leakage while maintaining fast switching speeds
Solution Approach 2:
The drain region is segmented into multiple components: the main drain, laterally-diffused drain extensions extending beneath the gate, and drain contact regions. This segmentation allows for optimized electric field distribution, reducing peak fields that cause breakdown while maintaining low resistance for high current drive
2Ease of manufacture
If conventional planar MOSFET architecture is used, then manufacturing is simpler, but current drive is lower and leakage is higher
Solution Approach 1:
The patent employs vertical fins extending from the substrate surface, creating a three-dimensional structure that increases the effective channel width without proportionally increasing the footprint. This allows FinFETs to achieve higher current drive compared to planar devices while maintaining compatibility with standard CMOS fabrication processes
Solution Approach 2:
The laterally-diffused drain extensions are nested beneath the gate electrode, with the gate overlying both the fin and the drain extension. This nested configuration allows the drain to be positioned in a region of lower electric field stress while maintaining electrical connection, reducing breakdown risk without adding external components
3Manufacturing precision
If gate insulator thickness is reduced for scaling, then device density increases, but susceptibility to hot carrier damage increases
Solution Approach 1:
The patent introduces a lightly-doped drift region as an intermediary between the heavily-doped drain and the channel. This drift region acts as a buffer that reduces peak electric fields and hot carrier generation, protecting the thin gate insulator from damage while allowing continued scaling
Solution Approach 2:
The patent modifies the doping profile in the drain region, creating a graded transition from the heavily-doped drain contact through a lightly-doped drift region to the intrinsic or lightly-doped channel. This parameter change in doping concentration progressively reduces electric field strength, minimizing hot carrier effects while maintaining device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The gate extension structure enhances the breakdown voltage characteristics and current drive of LDMOS FinFETs, reducing susceptibility to hot carrier-induced damage and improving reliability, as evidenced by simulated electrical performance comparisons.
Implementation Method 1
Incorporation of a gate extension and a blocking layer in LDMOS FinFETs to mitigate performance degradation by influencing electric field distribution and reducing hot carrier injection
Implementation Method 2
The field insulator material is disposed directly above the body region and surrounds a lower portion of the semiconductive fin
Data Source
AI summary
A semiconductor device and methods of forming the same include a semiconductive fin protruding vertically from a body region and extending along a first direction, an insulator material above the body region and surrounding a lower portion of the fin, and a gap region between first and second ends of the semiconductive fin where at least a top portion of the semiconductive fin is absent. The device includes current terminals coupled to first and second ends of the fin, and a gate electrode and a gate extension coupled to the fin. The gate electrode surrounds the top portion of the semiconductive fin and is separated from the semiconductive by a gate insulator material. The gate extension has a first end adjacent to the gate electrode and a second end above the body region within the gap region.