FinFET Parasitic Capacitance Reduction via Gate Extraction
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Solution Overview
Problem
The complexity of manufacturing FinFETs increases with scaling down in IC technology, requiring advancements in processing and manufacturing to improve AC performance without sacrificing DC performance and reduce capacitance between metal gate contacts and source/drain contacts.
Innovation Solution
The method involves forming semiconductor fins, using a gate-last process with sacrificial layers and spacers, and epitaxial growth of source/drain regions, along with a capping layer to reduce parasitic capacitance, allowing for higher frequency operation and improved AC performance without compromising DC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down is performed to increase functional density, then productivity and cost efficiency are improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into multiple sequential steps including forming sacrificial layers, forming spacers, selective etching, and epitaxial growth. Each step processes specific regions independently, allowing complex FinFET structures to be built through manageable segments rather than attempting monolithic fabrication.
Solution Approach 2:
Sacrificial layers are formed in advance before the actual FinFET structure is built. These preliminary layers guide subsequent processing steps and are removed after serving their templating function, enabling precise fin formation without requiring direct patterning of the final structure.
2Reliability
If conventional FinFET manufacturing is used, then DC performance is maintained, but AC performance is limited due to parasitic capacitance
Solution Approach 1:
The dummy gate electrode, which contributes to parasitic capacitance, is selectively removed from regions where source/drain contacts are formed. This extraction of the problematic component eliminates the source of parasitic capacitance while preserving the gate structure in regions where it is needed for transistor operation, thereby improving AC performance without sacrificing DC characteristics.
Solution Approach 2:
The gate electrode structure is made non-uniform: it is present over channel regions to maintain DC performance but removed over contact regions to reduce parasitic capacitance. This local differentiation allows the structure to optimize both AC and DC performance in their respective regions simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the AC performance of FinFETs by reducing capacitance, enabling higher frequency operation and improving the performance of devices like ring oscillators without affecting DC performance.
Implementation Method 1
implanting the semiconductor fins to form well regions
Implementation Method 2
performing an epitaxy to regrow source/drain regions
Data Source
AI summary
A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.