FinFET Gate And Fin Width Layout For Lower Resistance
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with fine patterns and three-dimensional channel structures poses challenges in achieving improved electrical and reliability characteristics, particularly in reducing resistance and parasitic capacitance due to the scaling down of transistors.
Innovation Solution
The method involves forming semiconductor structures with varying widths in different regions, including a first region with a wider channel width and a second region with a narrower width, and forming gate structures by depositing gate dielectric and gate electrodes in gap regions created by removing sacrificial gate patterns, along with epitaxial growth of source/drain regions to optimize resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the width of the semiconductor structure is reduced to achieve fine patterns and high integration, then the degree of integration is improved, but the resistance in the channel region increases
Solution Approach 1:
The semiconductor structure is designed with different widths in different regions: a first region with a first width and a second region with a second width that is smaller than the first width. This local variation in dimensions allows the channel region to maintain lower resistance while other regions achieve the fine pattern requirements for high integration.
2Productivity
If the size of planar MOSFETs is reduced to achieve fine patterns, then the degree of integration is improved, but parasitic capacitance increases
Solution Approach 1:
The invention transitions from planar MOSFETs to FinFETs with a three-dimensional channel structure. By adding the vertical dimension with fins extending from the substrate, the device achieves fine pattern dimensions in the planar view while maintaining effective channel area and reducing parasitic capacitance through the 3D structure.
3Manufacturing precision
If the width of the semiconductor structure is uniformly reduced, then fine patterns are achieved, but the resistance in the channel region increases
Solution Approach 1:
The semiconductor structure is designed with different widths in different regions: a first region with a first width and a second region with a second width that is smaller than the first width. This local variation in dimensions allows the channel region to maintain lower resistance while other regions achieve the fine pattern requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical characteristics by reducing resistance in the channel region and parasitic capacitance, thereby improving the overall performance and reliability of semiconductor devices.
Implementation Method 1
forming at least one gap region by removing the sacrificial gate pattern
Implementation Method 2
forming a gate structure by depositing a gate dielectric layer and a gate electrode in the at least one gap region
Implementation Method 3
performing an epitaxial growth process to form one or more source/drain regions on the active fin
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a semiconductor structure extending from a substrate in a first direction and having first and second regions; forming a sacrificial gate pattern intersecting the first region of the semiconductor structure and extending in a second direction perpendicular to the first direction; reducing a width in the second direction of the second region of the semiconductor structure exposed to at least one side of the sacrificial gate pattern; forming at least one recess portion by removing a portion of the second region of the semiconductor structure; forming one or more source/drain regions in the recess portion of the semiconductor structure on at least one side of the sacrificial gate pattern; forming at least one gap region by removing the sacrificial gate pattern; and forming a gate structure by depositing a gate dielectric layer and a gate electrode in the gap region.