FinFET Gate Line Geometry for Lower Parasitic Capacitance
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Solution Overview
Problem
As integrated circuit devices are downscaled, there is a need to improve the performance and reliability of field-effect transistors while reducing power consumption, particularly by minimizing parasitic capacitance between adjacent conductive regions.
Innovation Solution
The integrated circuit device incorporates a fin-type active region with a gate line that intersects it, featuring a gate dielectric film in contact with the gate line's lower surface and sidewalls. The gate upper surface has a portion with a decreasing distance from the substrate as the distance between the gate upper surface and the gate dielectric film decreases, and this configuration is enhanced by a capping insulating pattern that includes side insulating portions closer to the substrate than the gate upper surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If integrated circuit devices are downscaled to increase integration density, then device size is reduced, but parasitic capacitance between adjacent conductive regions increases
Solution Approach 1:
An insulating spacer is introduced as an intermediary material between the gate electrode and the source/drain electrodes. This spacer physically separates the conductive regions that would otherwise be in close proximity, thereby reducing parasitic capacitance while maintaining the downscaled device dimensions
Solution Approach 2:
The gate electrode is configured with a sloped or angled upper surface rather than a flat horizontal surface. This dimensional change in the gate electrode geometry creates increased vertical separation between the gate and source/drain regions, reducing parasitic capacitance without increasing the horizontal footprint of the device
2Reliability
If the gate electrode is positioned closer to the source/drain electrodes to improve transistor control, then gate control is enhanced, but parasitic capacitance increases
Solution Approach 1:
The insulating spacer is applied selectively at specific locations where the gate electrode interfaces with the source/drain electrodes. This localized insulation provides targeted parasitic capacitance reduction at the critical overlap regions while maintaining close proximity for gate control in other areas
Solution Approach 2:
The gate electrode upper surface is designed with an asymmetric slope angle rather than a symmetric flat surface. This asymmetric geometry optimizes the balance between maintaining sufficient gate control over the channel and creating adequate separation from the source/drain electrodes to minimize parasitic capacitance
3Length of stationary object
If the distance between gate upper surface and substrate is reduced to decrease device height, then device height is reduced, but parasitic capacitance between gate and substrate increases
Solution Approach 1:
The gate electrode upper surface is segmented into different zones with varying slopes or angles. The portion adjacent to the source/drain electrodes has a steeper slope creating greater separation, while the central portion maintains a smaller height to control overall device height. This segmentation allows simultaneous optimization of both parameters
Data Source
AI summary
An integrated circuit device includes a substrate; a fin-type active region that extends in a first horizontal direction on the substrate; a gate line on the fin-type active region, wherein the gate line extends in a second horizontal direction that intersects the first horizontal direction; and a gate dielectric film that is in contact with a lower surface and opposite sidewalls of the gate line, wherein a gate upper surface of the gate line includes a portion that has a decreasing distance from the substrate in a vertical direction as a distance between the portion of the gate upper surface of the gate line and the gate dielectric film in the first horizontal direction decreases.