FinFET Metal Gate Glue Layer for Leakage and Etch Control
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Solution Overview
Problem
In the semiconductor industry, FinFET devices face challenges in reducing metal gate leakage and preserving critical dimensions and sidewall profiles during advanced processing nodes, where the distance between adjacent metal gates becomes increasingly close, leading to reliability issues.
Innovation Solution
The method involves forming a gate dielectric layer, work function layers, and a glue layer with multiple sub-layers, where the glue layer includes a stack of tantalum nitride and titanium nitride, allowing for precise control of the metal gate height and preventing over-etching, thereby reducing damage to the metal gate and maintaining the integrity of the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent metal gates is reduced to increase integration density, then more components can be integrated into a given area, but metal gate leakage increases and reliability deteriorates
Solution Approach 1:
A glue layer comprising multiple sub-layers (first sub-layer and second sub-layer with different etch selectivities) is introduced as an intermediary between the metal gate and the gate dielectric layer. This intermediary structure enables precise control of metal gate height through selective etching processes, allowing for accurate positioning that reduces metal gate leakage while maintaining high integration density.
Solution Approach 2:
The patent utilizes changes in etch selectivity parameters between different sub-layers of the glue layer to achieve precise control over metal gate dimensions. By employing materials with different etch selectivities, the process can selectively remove portions of the glue layer to precisely define the metal gate height and critical dimensions, thereby reducing leakage without compromising integration density.
2Manufacturing precision
If etching processes are used to form metal gates, then precise control of metal gate height is achieved, but over-etching damages the metal gate structure
Solution Approach 1:
The glue layer acts as a cushioning layer that protects the metal gate from over-etching damage. The multiple sub-layers with different etch selectivities are designed to be removed in a controlled sequence, with the second sub-layer providing protection to the metal gate during the etching process. This beforehand cushioning prevents direct exposure of the metal gate to aggressive etching conditions that would cause damage.
Solution Approach 2:
The glue layer serves as an intermediary protective barrier between the etching process and the metal gate. By selectively removing portions of this intermediary layer, precise control of metal gate height is achieved while the remaining portions continue to protect the metal gate from damage during subsequent processing steps.
3Productivity
If advanced processing nodes are used to reduce feature size, then integration density improves, but critical dimensions and sidewall profiles become difficult to preserve
Solution Approach 1:
The patent employs parameter changes in material composition and etch selectivity to maintain manufacturing precision at advanced nodes. By carefully selecting materials for the glue layer sub-layers with appropriate etch selectivity ratios, the process can achieve precise control of critical dimensions even as feature sizes are reduced to increase integration density.
Solution Approach 2:
The glue layer is segmented into multiple sub-layers with different functions and etch selectivities. This segmentation allows for independent optimization of each sub-layer's properties to address specific challenges of advanced processing nodes, enabling precise control of critical dimensions and sidewall profiles while maintaining high integration density.
Data Source
AI summary
A semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes second spacers over the semiconductor fin. The second spacers vertically extend farther from the semiconductor fin than the first spacers. The semiconductor device includes a metal gate over the semiconductor fin, the metal gate is sandwiched by the first spacers. The metal gate includes a glue layer that contains tantalum nitride.