FinFET Gate Hard Mask Structure for Void-Free Core-Shell Formation
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving void-free core-shell hard mask formation over gate electrodes in FinFETs, particularly in advanced technology nodes, which affects the integration density and performance of electronic components.
Innovation Solution
A method is developed for forming a void-free core-shell hard mask over gate electrodes in FinFETs, involving the use of a gate-last process and specific materials and deposition techniques to ensure precise patterning and integration of semiconductor layers, including the formation of gate dielectric layers and gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition techniques are used to form hard mask over gate electrodes, then the manufacturing process is simpler, but voids form in the hard mask structure
Solution Approach 1:
The hard mask formation process is divided into multiple deposition stages: first depositing a liner layer, then a core material layer, and finally a shell material layer. This segmented approach ensures complete coverage and eliminates voids by building the structure incrementally with each layer serving a specific function.
Solution Approach 2:
A liner layer is deposited first as a preliminary action before forming the core and shell layers. This liner layer prepares the surface and ensures proper adhesion and coverage in subsequent deposition steps, preventing void formation in the final hard mask structure.
2Productivity
If integration density is increased by reducing minimum feature size, then more components can be integrated into a given area, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent changes the material parameters and deposition parameters (temperature, pressure, flow rates) to achieve precise control over the hard mask formation process. By optimizing these parameters, the process can accommodate reduced feature sizes while maintaining the required manufacturing precision for advanced technology nodes.
3Manufacturing precision
If void-free hard mask formation is achieved through multiple deposition layers, then manufacturing precision improves, but the number of process steps increases
Solution Approach 1:
Multiple deposition operations are merged into a single continuous process sequence within the same deposition chamber. The liner, core, and shell layers are deposited sequentially without breaking the vacuum or moving the substrate between chambers, reducing overall process time and maintaining high manufacturing throughput while achieving void-free structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables improved integration density and performance of FinFETs by ensuring void-free core-shell hard mask formation, enhancing the manufacturing process and reducing defects in semiconductor devices.
Implementation Method 1
performing a crystallization process on the first liner layer and the second liner layer
Implementation Method 2
specific materials and deposition techniques to ensure precise patterning
Implementation Method 3
specific materials and deposition techniques to ensure precise patterning
Data Source
AI summary
Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.