FinFET Gate Stack Layout for Uniform Height and Lower Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing fin-type field effect transistor (FinFET) devices due to the complexity of achieving uniform gate heights across different regions, which affects device performance and increases manufacturing costs.
Innovation Solution
The method involves patterning fins with varying spacings to form isolation structures of different heights, followed by a planarization process using chemical mechanical polish (CMP) to ensure uniform gate heights, thereby controlling gate heights and reducing parasitic capacitance across the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fins are patterned with varying spacings to form isolation structures of different heights, then device performance is improved through better control of parasitic capacitance, but manufacturing complexity increases due to the need for multiple patterning steps and precise CMP planarization
Solution Approach 1:
The patent applies local quality by creating isolation structures with different heights in different regions of the substrate. Fins are patterned with varying spacings, and isolation structures are formed to different heights based on local requirements, allowing optimization of parasitic capacitance control in specific areas without uniformly increasing complexity across the entire device.
Solution Approach 2:
The patent employs preliminary action through the planarization process using chemical mechanical polishing (CMP). The CMP process is performed in advance to establish a uniform gate height reference plane before subsequent gate formation steps, ensuring that varying isolation structure heights do not compromise gate uniformity. This preliminary planarization enables the later formation of consistent gate structures despite the non-uniform isolation landscape.
2Manufacturing precision
If a planarization process using CMP is employed to ensure uniform gate heights, then manufacturing precision is improved, but production time and cost increase
Solution Approach 1:
The patent utilizes parameter changes by varying the spacing between fins in different regions, which directly influences the height of the isolation structures formed between them. By controlling the fin spacing parameter, the isolation structure heights are adjusted to achieve optimal parasitic capacitance characteristics. The CMP process then compensates for these height variations to achieve uniform gate formation, balancing precision requirements with process efficiency.
3Object-generated harmful factors
If isolation structures of different heights are formed, then parasitic capacitance is reduced through better electrical isolation, but the ease of manufacture decreases due to additional process steps
Solution Approach 1:
The patent applies segmentation by dividing the substrate into different regions with varying fin spacings and isolation structure heights. This segmentation allows tailored electrical isolation in different areas, optimizing parasitic capacitance reduction where needed while maintaining simpler structures in other regions. The segmented approach enables selective optimization without requiring complex high-precision processes across the entire wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by maintaining consistent gate heights and reducing manufacturing costs, while avoiding excess parasitic capacitance, thus enhancing the overall efficiency of FinFET device production.
Implementation Method 1
a planarization process using chemical mechanical polish (CMP) to ensure uniform gate heights
Data Source
AI summary
The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.