FinFET Gate Electrode Height Optimization for Capacitance Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing effective capacitance, which affects their AC performance and reliability, particularly in multigate transistors where the scaling of semiconductor devices is limited by the short channel effect and increased gate length.
Innovation Solution
The proposed solution involves a semiconductor device design with a deep trench portion that increases the height of the gate electrode, utilizing a fin-type pattern with a field-insulating layer and a gate electrode that intersects the fin-type pattern, thereby reducing the effective capacitance by adjusting the thickness and height of the field-insulating layers to minimize the overlap area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length is increased to suppress short channel effect, then the electric potential control is improved, but the device density and scaling are reduced
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional multigate structures (FinFET, GAA, nanosheet). By adding vertical dimensions and wrapping the gate around the channel in multiple directions, the device achieves superior short channel effect suppression without increasing the planar footprint, thereby maintaining high device density while improving electrical control.
Solution Approach 2:
The gate structure is nested around the channel in a wraparound configuration, with the gate electrode surrounding the channel region in multiple directions. This nested arrangement maximizes the gate's control over the channel potential while minimizing the device area, resolving the contradiction between reliability and productivity.
2Reliability
If the trench depth is increased to reduce gate capacitance, then the AC performance is improved, but the manufacturing complexity increases
Solution Approach 1:
The deep trench structure is segmented into multiple regions with different insulating materials (first field-insulating layer and second field-insulating layer with different dielectric constants). This segmentation allows the patent to achieve the desired capacitance reduction through material properties rather than solely relying on increased trench depth, thereby reducing manufacturing complexity while maintaining AC performance improvements.
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) of the field-insulating layers to control the capacitance effect. By using materials with different dielectric constants in different regions, the patent achieves capacitance modulation without requiring proportionally deeper trenches, thus balancing AC performance improvement with manufacturing feasibility.
Data Source
AI summary
A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench formed in contact with the first sidewall; a second trench formed in contact with the second sidewall; a first field insulating layer partially filling the first trench; and a second field insulating layer partially filling the second trench and a second field insulating layer partially filling the second trench. The second field insulating layer includes a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field insulating layer. The device further includes a gate electrode on the first fin-type pattern, the first field insulating layer and the second field insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.