FinFET Gate Stack Layout for Uniform Gate Height Control
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing fin-type field effect transistors (FinFETs) due to the complexity of achieving uniform gate heights across different regions, which affects device performance and increases manufacturing costs.
Innovation Solution
The method involves patterning fins with varying spacings to form isolation structures of different heights, using a dummy gate layer with a planarization process to ensure uniform gate heights across regions, and replacing dummy gates with metallic gate stacks, thereby controlling gate heights and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fins are patterned with varying spacings to form isolation structures of different heights, then device performance is improved through better electrical isolation, but manufacturing precision requirements increase due to the need for uniform gate heights across different regions
Solution Approach 1:
A dummy gate layer is formed over the substrate and fins before the actual gate structure is created. This dummy gate layer serves as a preliminary structure that is subsequently planarized to ensure uniform gate heights across regions with different fin spacings, resolving the contradiction between electrical isolation needs and manufacturing precision requirements
Solution Approach 2:
The dummy gate layer acts as an intermediary element between the isolation structures of different heights and the final gate structure. By planarizing this intermediate layer, the patent achieves uniform gate heights while maintaining the beneficial electrical isolation provided by the varying isolation structure heights
2Manufacturing precision
If dummy gate layer with planarization process is used to ensure uniform gate heights, then manufacturing precision is improved, but device complexity increases due to additional process steps
Solution Approach 1:
The dummy gate layer serves multiple functions: it acts as a sacrificial structure during processing, provides a planarization reference surface, and ultimately becomes part of the final gate structure. This multi-functionality reduces the need for separate structures and processes, offsetting the added complexity with process integration benefits
Solution Approach 2:
The patent combines the dummy gate formation with the isolation structure creation process. The dummy gate layer is formed over the entire surface including both the fins and the isolation structures, merging multiple structure creation steps into a more integrated process flow that reduces overall device complexity
3Reliability
If isolation structures of different heights are formed, then electrical isolation is improved, but parasitic capacitance increases due to larger gate area
Solution Approach 1:
The isolation structures are given different heights based on their local requirements - higher isolation structures in regions where greater electrical isolation is needed, and lower isolation structures where minimal isolation suffices. This local differentiation optimizes electrical isolation while minimizing the total gate area and associated parasitic capacitance
Data Source
AI summary
The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.