3D FinFET Gate Electrode Height Reduction for Integration Density
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Solution Overview
Problem
The integration density of semiconductor memory devices is limited by the cost of process equipment, necessitating innovative approaches to reduce pattern dimensions and enhance integration without increasing costs.
Innovation Solution
The semiconductor device design includes a substrate with a cell array region and a peripheral circuit region, featuring cell and peripheral gate electrodes with distinct structures and materials, and source/drain regions, which reduces the height difference between these regions, allowing for increased integration density and simplified wiring processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If process equipment cost is reduced to increase integration density, then manufacturing cost decreases, but manufacturing precision deteriorates
Solution Approach 1:
The patent transitions from planar 2D transistor structures to 3D vertical structures by forming gate electrodes that wrap around fins and source/drain regions extending in multiple levels. This dimensional change increases integration density without requiring proportional reductions in lithographic pattern dimensions, thereby maintaining manufacturing precision while improving productivity.
Solution Approach 2:
The patent implements nested structures where gate electrodes are positioned within trenches formed in the substrate, and source/drain regions are formed within fins that extend from the substrate. The gate electrode structure is nested within the substrate matrix, allowing multiple functional regions (cell array and peripheral circuit) to be integrated in a compact three-dimensional arrangement.
2Productivity
If pattern dimensions are reduced to increase integration, then integration density increases, but device complexity increases
Solution Approach 1:
The patent divides the substrate into distinct functional segments: a cell array region containing memory cells and a peripheral circuit region containing control circuits. Each region has its own optimized transistor structure with specific gate electrode configurations. This segmentation allows independent optimization of each region's performance while maintaining overall integration density.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the cell array region uses a first transistor structure with specific gate electrode depth and width ratios optimized for memory storage, while the peripheral circuit region uses a second transistor structure with different dimensions optimized for control logic operations. This local differentiation reduces overall device complexity by allowing region-specific optimization rather than requiring all regions to use identical complex structures.
Data Source
AI summary
A semiconductor device may include a substrate having a first region and a second region on a surface thereof, and a first semiconductor fin on the first region of the substrate with the first semiconductor fin including a first trench therethrough. A first gate electrode may be provided in the first trench, and first and second source/drain regions may be provided in the first semiconductor fin, with the first gate electrode between the first and second source/drain regions. A second semiconductor fin may be provided on the second region of the substrate with the second semiconductor fin including a second trench therethrough, a second gate electrode may be provided in the second trench, and third and fourth source/drain regions may be provided in the second semiconductor fin with the second gate electrode being between the third and fourth source/drain regions.