Uniform FinFET Gate Height via Dielectric Spacer Mandrels
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Solution Overview
Problem
The dimensional uniformity of gate heights in finFET semiconductor devices is compromised due to varying pattern densities across the chip, leading to reliability issues and increased process complexities.
Innovation Solution
A method involving the formation of fins etched from a semiconductor substrate, covered by oxide and nitride layers, with a fill material deposited between them, where the nitride layer is removed to create a gap, and re-entrant geometry is addressed through etching techniques to ensure uniformity and planarity, allowing for consistent gate formation across varying device densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fins are formed in a substrate and gate stack is deposited, then finFET devices are fabricated, but gate height varies significantly within a single chip due to variation in pattern density
Solution Approach 1:
The patent applies preliminary action by forming mandrels and dielectric spacers before depositing the gate stack material. The mandrels are positioned to protrude through the nitride layer, and dielectric spacers are formed on their sidewalls prior to gate deposition. This preliminary structuring ensures that when the gate material is deposited, it conforms to the predetermined spacer geometry, thereby ensuring uniform gate height across regions with different fin densities before the actual gate formation occurs.
Solution Approach 2:
The patent uses dielectric spacers as intermediary structures between the fins and the gate. These spacers are formed by depositing dielectric material conformally on the sidewalls of mandrels, then selectively removing the mandrels. The spacers serve as temporary placeholders that define the gate boundary and ensure uniform gate height, and are later removed after gate formation to create the final gate structure with consistent dimensions across varying pattern densities.
2Adaptability or versatility
If areas of high pattern density include a plurality of fins whereas areas of low pattern density include one or two fins, then chip functionality is achieved, but gate height measured in areas of low pattern density is lower than in areas of high pattern density
Solution Approach 1:
The patent applies local quality by forming mandrels and dielectric spacers in a non-uniform pattern that matches the local fin density requirements. In high-density areas, multiple mandrels are formed close together, while in low-density areas, fewer mandrels are spaced farther apart. The dielectric spacers are then formed on each mandrel's sidewall, ensuring that each local region receives the appropriate gate structure definition. This localized structuring allows the gate height to be uniformly controlled in each specific area regardless of the overall pattern density variation across the chip.
3Ease of manufacture
If gate first process flow is used including forming fins, depositing gate stack, and etching final gate structures, then fabrication is completed, but large variations in gate height are produced
Solution Approach 1:
The patent introduces dielectric spacers as intermediary structures in the gate first process flow. After fins are formed and before the final gate etch, mandrels are deposited and dielectric material is conformally deposited on their sidewalls. The mandrels are then selectively removed, leaving dielectric spacers that serve as precise etch stop references. When the gate stack is subsequently etched, these spacers ensure that the gate height is uniformly defined across the entire chip, eliminating the large variations that would otherwise occur in conventional gate first processes.
4Ease of manufacture
If replacement gate process flow is used with dummy gate stack, then fabrication is completed, but thickness of gate stack or dummy gate stack varies between areas of high and low pattern density
Solution Approach 1:
The patent applies preliminary action by forming dielectric spacers on mandrel sidewalls before depositing the dummy gate stack material. The mandrels are positioned to protrude through the nitride layer, and the dielectric spacers are formed conformally on their sidewalls prior to dummy gate deposition. This preliminary structuring creates physical boundaries that constrain the dummy gate material thickness, ensuring uniform gate stack thickness across areas of both high and low pattern density before the replacement gate process proceeds.
Data Source
AI summary
A structure including a first plurality of fins and a second plurality of fins etched from a semiconductor substrate, and a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, the fill material does not contact either the first plurality of fins or the second plurality of fins.