FinFET Gate Structure Using High-k Layers for Multi-Vt Patterning
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Solution Overview
Problem
As IC technology nodes shrink, existing FinFETs with multiple threshold voltages face challenges in gate fill window and conformity requirements, leading to increased complexity and cost in fabrication, particularly below the N5 generation.
Innovation Solution
The method involves the deposition and patterning of multiple high-k dielectric layers before work function metal layers, improving process tolerance and yield by simplifying the fabrication process and reducing production costs through the use of high-k dielectric layers for multiple threshold voltage tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple threshold voltages are implemented using existing FinFETs with metal gate electrodes, then different threshold voltages can be achieved through work function values of metal gate electrodes, but gate fill window and conformity requirements become increasingly difficult to meet as IC technology nodes shrink below N5 generation
Solution Approach 1:
The gate structure is segmented into multiple high-k dielectric layers with different thicknesses instead of using a single metal gate layer. This segmentation allows different threshold voltages to be achieved through varying dielectric thicknesses, which are easier to control with standard lithography processes, thereby resolving the gate fill window and conformity issues at advanced technology nodes
Solution Approach 2:
The invention changes the controlling parameter from metal gate work function to high-k dielectric layer thickness. By adjusting the thickness of high-k dielectric layers, multiple threshold voltages can be achieved with better process control and larger process windows, eliminating the manufacturing precision challenges associated with metal gate electrode work function tuning
2Reliability
If existing FinFETs with metal gate electrodes are used for multiple threshold voltages, then device performance can be improved, but fabrication complexity and production costs increase
Solution Approach 1:
The high-k dielectric layer structure serves multiple functions: it provides the gate dielectric function, enables multiple threshold voltages through thickness variation, and can be patterned using standard lithography. This multi-functionality simplifies the overall fabrication process compared to metal gate replacement processes, reducing both fabrication complexity and production costs while maintaining device performance
Solution Approach 2:
The high-k dielectric layers are formed using atomic layer deposition (ALD) with self-aligned processes, where the dielectric layers automatically conform to the underlying structures without requiring additional alignment steps. This self-service capability reduces process complexity and improves yield compared to metal gate electrode processes that require precise alignment and replacement steps
3Adaptability or versatility
If multiple threshold voltages are achieved using existing FinFET processes, then device functionality is adequate, but yield and gap-fill capability deteriorate at advanced technology nodes
Solution Approach 1:
The invention changes from controlling threshold voltage via metal gate work function to controlling it via high-k dielectric layer thickness. This parameter change enables better gap-fill capability because ALD processes can uniformly deposit thin dielectric layers across varying topographies, and the thickness control provides sharper threshold voltage differentiation, thereby improving yield at advanced technology nodes
Solution Approach 2:
The invention replaces the mechanical/metallurgical process of metal gate electrode deposition and work function tuning with a dielectric deposition process using ALD. This substitution provides better conformality and gap-fill capability because dielectric materials can be deposited uniformly in high-aspect-ratio structures, improving yield without sacrificing multiple threshold voltage functionality
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.