FinFET Gate Insulation for Contact Alignment
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Solution Overview
Problem
Conventional processing methods for integrated circuit devices, such as FinFETs, are time, material, and machine intensive, and prone to defect formation due to complex steps like chamfering and self-aligned contact processing, which also introduce alignment challenges between gate and source/drain contacts.
Innovation Solution
The method involves patterning parallel fins and sacrificial gates, forming insulator layers, and using strategically placed sidewall insulators and spacers to reduce processing steps and accommodate contact misalignment, thereby avoiding chamfering and complex metallization processes, and allowing for the formation of gate and source/drain structures with multiple insulator layers and conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional chamfering and self-aligned contact processing steps are used, then gate and source/drain contact alignment is achieved, but processing time, material consumption, and machine usage increase significantly
Solution Approach 1:
The gate structure is divided into multiple segments with different heights, creating stepped regions that serve as built-in alignment references for source/drain contacts. This segmentation eliminates the need for separate chamfering and self-aligned contact processing steps, reducing processing complexity while maintaining alignment precision.
Solution Approach 2:
The gate structure is pre-formed with stepped regions and insulating layers before contact formation. These preliminary structural features provide built-in alignment guidance, eliminating the need for subsequent alignment-critical processing steps like chamfering and self-aligned contact deposition.
2Manufacturing precision
If multiple processing steps including chamfering and self-aligned contact processing are performed, then contact alignment is improved, but defect formation opportunities increase
Solution Approach 1:
By segmenting the gate structure into stepped regions with different heights, the patent creates inherent alignment features that guide contact formation. This reduces the number of separate processing steps required, thereby reducing cumulative defect opportunities while maintaining alignment precision.
Solution Approach 2:
The gate structure itself provides the alignment reference features through its stepped configuration. The structure serves its own alignment function without requiring additional dedicated alignment steps, reducing process complexity and defect formation opportunities.
3Ease of manufacture
If conventional processing methods are used, then gate structures are formed, but processing complexity and resource consumption increase
Solution Approach 1:
The patent merges gate formation and contact alignment functions into a single integrated process. The stepped gate structure with insulating layers performs both gate function and alignment reference function simultaneously, eliminating the need for separate chamfering and self-aligned contact processing steps.
Solution Approach 2:
The gate structure is designed to serve multiple functions: electrical gating function, mechanical support, and alignment reference for contacts. This multi-functionality reduces the number of dedicated processing steps required, simplifying the overall manufacturing process while maintaining device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and intensity of processing, minimizes defect formation, and efficiently forms integrated circuit structures with improved alignment and reduced SAC processing, leading to more efficient and reliable integrated circuit manufacturing.
Implementation Method 1
Multiple insulator layers are positioned between the gate structures and the lower source/drain contacts
Implementation Method 2
epitaxially grow source/drain structures on the fins between the sacrificial gates
Data Source
AI summary
Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.