FinFET Gate Interface Structure to Suppress Germanium Diffusion
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Solution Overview
Problem
Current semiconductor devices, particularly FinFETs, face challenges in enhancing drive currents due to limitations in charge mobility and interfacial issues between channel regions and interfacial layers, which affect electron and hole mobility and device reliability.
Innovation Solution
Incorporating a semiconductive protection layer formed by molecular beam epitaxy (MBE) between the channel region and the gate dielectric layer, with a low-temperature process to suppress germanium diffusion and reduce interface state density, and employing a post-gate forming gas annealing process to improve interfacial properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate dielectric layer is formed directly on the channel region, then the device structure is simple, but interface state density increases and electron mobility decreases
Solution Approach 1:
An interfacial layer is introduced between the gate dielectric layer and the channel region to serve as an intermediary. This interfacial layer has a gradient composition with higher germanium content near the channel region, which reduces interface state density and improves electron mobility while maintaining device reliability.
2Reliability
If high temperature processing is used to form the gate dielectric layer, then the dielectric properties are improved, but germanium diffusion increases and interface quality deteriorates
Solution Approach 1:
The processing temperature is reduced to below 300°C when forming the gate dielectric layer on the interfacial layer. This temperature parameter change prevents germanium diffusion that would occur at higher temperatures, maintaining interface quality while still achieving good dielectric properties.
3Manufacturing precision
If germanium diffusion is suppressed during gate dielectric formation, then interface quality is maintained, but the dielectric layer formation process becomes more complex
Solution Approach 1:
The interfacial layer with gradient composition is formed in advance before depositing the gate dielectric layer. This preliminary action creates a diffusion barrier that prevents germanium migration during subsequent dielectric formation, maintaining interface quality without requiring complex in-situ control measures.
4Ease of manufacture
If the channel region is exposed during gate formation, then process access is easy, but germanium oxidation occurs and interface traps increase
Solution Approach 1:
The interfacial layer serves as a protective intermediary between the channel region and the gate dielectric layer. It prevents direct exposure and oxidation of the channel region while allowing conformal deposition of the dielectric layer, thereby reducing interface traps without compromising process accessibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electron mobility, reduces bias temperature instability, and improves device reliability by minimizing germanium oxidation and interface traps, thereby increasing drive currents and stability of semiconductor devices.
Implementation Method 1
a semiconductive protection layer formed by molecular beam epitaxy (MBE) between the channel region and the gate dielectric layer
Implementation Method 2
with a low-temperature process to suppress germanium diffusion
Implementation Method 3
employing a post-gate forming gas annealing process to improve interfacial properties
Implementation Method 4
enhances electron mobility, reduces bias temperature instability, and improves device reliability by minimizing germanium oxidation
Data Source
AI summary
A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.