3D FinFET Gate Structure With Internal Spacers for Reliability
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Solution Overview
Problem
As semiconductor devices become increasingly integrated for high performance and multifunctionality, there is a need for improved electrical properties and reliability, particularly in FinFETs with three-dimensional channel structures to overcome limitations due to size reduction of planar metal oxide semiconductor field-effect transistors (MOSFETs).
Innovation Solution
A semiconductor device is designed with a substrate, active region, channel layers, a gate structure including a gate dielectric layer and gate electrode, and source/drain regions, where the gate structure has an upper portion and lower portions with inclined side surfaces, and internal spacer layers are used to enhance electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar metal oxide semiconductor field-effect transistors are used, then device integration is simplified, but electrical properties and reliability deteriorate due to size reduction limitations
Solution Approach 1:
The patent transitions from a planar two-dimensional channel structure to a three-dimensional FinFET structure with vertical channels extending from the substrate surface. This dimensional change enables better gate control over the channel and improves electrical properties by utilizing the third dimension (vertical direction) to overcome the limitations of size reduction in planar devices.
Solution Approach 2:
The channel region is segmented into multiple vertical fins or channels that extend upward from the substrate. This segmentation allows each fin to be independently controlled by the gate structure, improving overall device performance and reliability while maintaining compact integration.
2Productivity
If device integration is increased for high performance and multifunctionality, then productivity and functionality improve, but manufacturing precision and reliability worsen due to finer pattern dimensions
Solution Approach 1:
By moving to a three-dimensional FinFET structure, the patent achieves higher device integration and functionality without proportionally reducing lateral pattern dimensions. The vertical dimension provides additional control and performance headroom, allowing finer lateral features to be manufactured with better precision.
Solution Approach 2:
The patent changes key geometric parameters by introducing vertical channel depth and fin height as new dimensions for optimization. This allows performance improvement through vertical scaling rather than lateral scaling, thereby maintaining better manufacturing precision for lateral features while achieving higher integration.
3Reliability
If FinFET three-dimensional channel structure is implemented, then electrical properties improve, but device complexity increases
Solution Approach 1:
The patent implements the three-dimensional channel structure by creating vertical fins that extend from the substrate surface. This dimensional change provides superior gate control and improved electrical properties while maintaining a relatively systematic structure that can be manufactured using established semiconductor fabrication processes.
Solution Approach 2:
The FinFET structure serves multiple functions simultaneously: it provides enhanced gate control, increases effective channel width for higher current drive, and maintains compatibility with standard CMOS fabrication processes. This multi-functionality justifies the increased structural complexity by delivering proportional performance benefits.
Data Source
AI summary
A semiconductor device includes an active region, a plurality of channel layers spaced apart from each other on the active region, a gate structure including a gate dielectric layer and a gate electrode, and source/drain regions on both sides of the gate structure. The gate structure includes an upper portion and lower portions. A first lower portion of the lower portions has a first lower surface, a first upper surface, and first and second side surfaces. Each of the first and second side surfaces includes a first inclined portion sloped at a first acute angle from the first lower surface and a second inclined portion sloped at a second acute angle from the first upper surface. The gate dielectric layer includes portions disposed between the gate electrode and the plurality of channel layers and between the gate electrode and the source/drain regions.