FinFET Gate Isolation Structure for Low-Capacitance CMG Trenches
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing capacitance and preventing metal extrusion issues in cut metal gate (CMG) processes, particularly due to the use of high-k dielectric materials which can lead to increased capacitance and damage during etching, when trying to replace high-k dielectric materials with low-k dielectric materials in CMG trenches.
Innovation Solution
A semiconductor structure and method involving a cut metal gate process where a low-k dielectric material is used in CMG trenches, and a nitrogen-containing treatment is applied to convert the low-k material into a solid dielectric feature with a higher nitrogen concentration, reducing capacitance and mitigating metal extrusion by using a dielectric layer with different materials and thicknesses to isolate metal gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If high-k dielectric material is used in gate dielectric layer, then effective gate thickness is improved, but gate leakage increases
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of a high-k dielectric layer (such as hafnium oxide) combined with an interfacial layer (such as silicon oxide). This composite structure allows the high-k material to provide effective gate thickness while the interfacial layer prevents direct contact between the metal gate and high-k dielectric, thereby reducing gate leakage currents.
Solution Approach 2:
An interfacial layer is introduced as an intermediary between the metal gate electrode and the high-k dielectric layer. This interfacial layer acts as a mediator that prevents direct interaction between the metal and high-k dielectric, reducing gate leakage while maintaining the electrical benefits of the high-k material.
2Object-generated harmful factors
If low-k dielectric material is used in CMG trenches, then capacitance is reduced, but metal extrusion issues occur during etching
Solution Approach 1:
A nitrogen-containing treatment is applied to the low-k dielectric material before the etching process. This preliminary action converts the low-k material into a nitrogen-rich solid that is more resistant to metal extrusion during subsequent etching operations, while still maintaining the low capacitance特性 required for device performance.
Solution Approach 2:
The patent changes the chemical composition parameters of the low-k dielectric material by introducing nitrogen through nitrogen-containing treatments. This parameter change transforms the material properties to resist metal extrusion while preserving the low-k dielectric characteristics needed for reduced capacitance.
3Productivity
If metal gate is fabricated last in RPG approach, then number of subsequent operations is reduced, but process complexity increases
Solution Approach 1:
The metal gate fabrication process is segmented into distinct stages: formation of the metal gate electrode, patterning to define gate regions, and selective removal in CMG trenches. This segmentation allows for better process control and integration with existing manufacturing flows, managing complexity while maintaining productivity benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance between metal gate structures and prevents metal extrusion issues by using a low-k dielectric material converted into a nitrogen-rich solid, ensuring reliable semiconductor performance and manufacturing integrity.
Implementation Method 1
a nitrogen-containing treatment is applied to convert the low-k material into a solid dielectric feature with a higher nitrogen concentration
Data Source
AI summary
A semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.