FinFET Gate Isolation via Segmented Comb Structure
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Solution Overview
Problem
Existing FinFET devices and manufacturing methods face challenges in achieving optimal physical and electrical isolation between closely adjacent gate strips, leading to increased leakage current and time-dependent dielectric breakdown.
Innovation Solution
A method for forming a FinFET device involving the creation of a comb-like insulating structure with protruding parts that penetrate through underlying fins, reducing fin residues and enhancing isolation between gate strips, utilizing a combination of etching processes and insulating layer deposition to achieve excellent physical and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation structures are used between gate strips, then manufacturing is simpler, but leakage current increases and dielectric breakdown resistance decreases
Solution Approach 1:
The isolation structure is segmented into multiple components: a base insulating layer, protruding parts extending between gate strips, and void regions. This segmentation allows each component to perform its function optimally - the base layer provides foundational isolation, the protruding parts create physical barriers, and the void regions eliminate conductive paths, collectively reducing leakage current while maintaining manufacturability
Solution Approach 2:
The isolation structure incorporates void regions (porous spaces) between the protruding parts and gate strips. These voids act as insulating regions that completely block electrical leakage paths. The porous configuration provides superior electrical isolation compared to solid insulating materials alone, as it eliminates continuous conductive paths while the remaining insulating material provides mechanical support
2Manufacturing precision
If simpler isolation structures are used, then manufacturing is easier, but fin residues increase and isolation quality decreases
Solution Approach 1:
The method performs preliminary actions by first forming the base insulating layer and protruding parts before creating the void regions. The protruding parts are formed to extend between gate strips, and then voids are created within these protruding parts. This preliminary configuration ensures that when voids are formed, the surrounding structure is already in place to provide proper isolation, eliminating the need for complex post-processing to remove fin residues
Solution Approach 2:
The method extracts and removes fin residues from within the protruding parts of the isolation structure. By specifically targeting and removing these residues, the patent ensures complete clearance of conductive material that would otherwise create leakage paths. This extraction process is integrated into the existing manufacturing flow, adding minimal complexity while dramatically improving isolation quality
3Reliability
If conventional etching processes are used, then processing is simpler, but leakage current paths are not effectively blocked
Solution Approach 1:
The etching process is divided into periodic stages: first etching to form the base insulating layer, then etching to create protruding parts, and finally etching to form void regions within the protruding parts. Each etching stage targets a specific feature, allowing precise control over the isolation structure's geometry. This periodic approach ensures that voids are completely formed to block leakage paths while the process remains integrated into standard manufacturing flows
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces leakage current and improves time-dependent dielectric breakdown characteristics by creating a void-free or void-containing comb-like insulating structure that isolates gate strips, ensuring better performance and reliability.
Implementation Method 1
utilizing a combination of etching processes and insulating layer deposition
Implementation Method 2
utilizing a combination of etching processes and insulating layer deposition
Data Source
AI summary
A method of forming a FinFET device includes following steps. A substrate is provided with a plurality of fins thereon, an isolation layer thereon covering lower portions of the fins, a plurality of dummy strips across the fins, and a dielectric layer aside the dummy strips. The dummy strips is cut to form a trench in the dielectric layer. A first insulating structure is formed in the trench, wherein first and second groups of the dummy strips are beside the first insulating structure. A dummy strip is removed from the first group of the dummy strips to form a first opening that exposes portions of the fins under the dummy strip. The portions of the fins are removed to form a plurality of second openings below the first opening, wherein each second opening has a middle-wide profile. A second insulating structure is formed in the first and second openings.