FinFET Gate Isolation Layout for Low-Resistance Source/Drain Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of chip area in semiconductor integrated circuits (ICs) leads to increased coupling effects between semiconductor devices, causing noise, signal delays, and logic errors. The continuous poly on oxide definition edge (CPODE) pattern, used to cut noise coupling paths, can squeeze source/drain contact openings, making it difficult to form silicide and increasing the resistance of the source/drain contact.
Innovation Solution
An impurity implantation process is performed on a dielectric layer where the CPODE pattern will be formed, creating a stress memorization technology (SMT) layer. This layer controls the profile of the adjacent CPODE pattern, preventing it from squeezing the source/drain contact opening and improving the process window for forming the source/drain contact and silicide, thereby reducing the resistance of the source/drain contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If CPODE pattern is formed to cut noise coupling paths, then noise coupling is reduced, but source/drain contact opening is squeezed making silicide formation difficult and resistance increases
Solution Approach 1:
The patent performs impurity implantation on the dielectric layer before forming the CPODE pattern. This preliminary action creates a stress memorization layer that will later control the CPODE profile to prevent squeezing of the source/drain contact opening, thus resolving the contradiction between noise coupling reduction and contact opening size maintenance
Solution Approach 2:
The patent changes the physical-chemical parameters of the dielectric layer by implanting impurities (such as nitrogen or carbon) to create a stress memorization technology layer. This parameter change enables the dielectric layer to control the CPODE profile and prevent harmful squeezing effects on the contact opening
2Object-affected harmful factors
If CPODE pattern is formed to cut noise coupling paths, then noise coupling is reduced, but process window for forming source/drain contact and silicide is reduced
Solution Approach 1:
The impurity implantation is performed as a preliminary action before CPODE formation to pre-establish the stress memorization layer. This ensures that when the CPODE pattern is subsequently formed, the profile is automatically controlled to maintain adequate process window for contact and silicide formation while still achieving noise coupling reduction
Solution Approach 2:
The stress memorization technology layer acts as an intermediary between the CPODE pattern formation process and the source/drain contact formation process. It mediates the interaction by controlling the CPODE profile to prevent squeezing, thereby maintaining ease of manufacture for subsequent contact and silicide formation steps
3Productivity
If chip area is scaled down to increase production efficiency, then production cost is reduced, but coupling effects between devices increase causing noise and signal delays
Solution Approach 1:
The patent extracts or removes the harmful coupling effects by introducing the CPODE pattern that cuts noise coupling paths between adjacent devices. The impurity implantation enhances this extraction by creating stress memorization that optimizes the CPODE profile for maximum coupling reduction while maintaining device performance
Solution Approach 2:
The patent changes the physical parameters of the dielectric layer through impurity implantation to create stress memorization. This parameter change enables the dielectric to actively control and reduce coupling effects between devices, allowing continued scaling while maintaining signal integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces the resistance of the source/drain contact by preventing the CPODE pattern from squeezing the contact opening, improving the formation of silicide, and enhancing the overall process window for contact formation.
Implementation Method 1
An impurity implantation process is performed on a dielectric layer where the CPODE pattern will be formed
Implementation Method 2
performing an annealing process to expand the doped first portion of the dielectric layer toward the gate trench
Data Source
AI summary
A method includes forming first and second gate stacks extending across a semiconductor fin on a substrate; forming source/drain regions in the semiconductor fin, wherein one of the source/drain region is between the first and second gate stacks; forming a dielectric layer laterally surrounding the first and second gate stacks; doping a portion of the dielectric layer between the first and second gate stacks with a dopant; removing the second gate stack to form a gate trench next to the doped first portion of the dielectric layer; performing an annealing process to expand the doped first portion of the dielectric layer toward the gate trench; forming an isolation structure in the gate trench and next to the expanded first portion of the dielectric layer; forming a source/drain contact extending through the dielectric layer to the one of the source/drain regions.