FinFET Gate Isolation Structure for Dummy Gate Removal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming non-planar transistor devices, such as FinFETs, face issues with residual dummy gate structures causing short circuits and undesired gate leakage due to processing variations, which are not fully addressed by current gate isolation techniques.
Innovation Solution
The method involves forming a gate isolation structure over dummy fins and isolation regions by further removing upper portions of dummy fins or isolation regions to ensure complete removal of residual dummy gate structures, allowing for electrical isolation of metal gate layers and preventing gate leakage, while tuning etching selectivity to control lateral etching and maintain critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate isolation techniques are used to remove dummy gate structures, then electrical isolation is improved, but residual dummy gate structures remain causing short circuits and gate leakage
Solution Approach 1:
The method performs preliminary removal of upper portions of dummy fins or isolation regions before forming the gate isolation structure. This preliminary action creates additional space and ensures that residual dummy gate structures are completely removed, preventing short circuits and gate leakage while maintaining electrical isolation.
Solution Approach 2:
The method extracts and removes the upper portions of dummy fins or isolation regions separately from the main gate isolation process. This extraction approach allows for complete removal of residual dummy gate structures that would otherwise cause electrical failures, ensuring reliable electrical isolation.
2Manufacturing precision
If etching is used to remove dummy structures, then complete removal is improved, but lateral etching occurs affecting critical dimensions
Solution Approach 1:
The method applies different etching conditions to different regions: aggressive etching is used locally on upper portions of dummy fins or isolation regions to ensure complete removal of dummy structures, while the main gate isolation structure uses controlled etching to maintain critical dimensions. This localized quality approach resolves the contradiction between complete removal and dimension control.
Solution Approach 2:
The etching process is segmented into two distinct stages: first removing upper portions of dummy fins/isolation regions with selective etching, then forming the gate isolation structure with controlled etching. This segmentation allows each stage to optimize for its specific goal without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents short circuits and gate leakage by ensuring complete removal of residual dummy gate structures, maintaining accurate critical dimensions, and enhancing the electrical isolation of metal gate layers in non-planar transistor devices.
Implementation Method 1
tuning etching selectivity to control lateral etching and maintain critical dimensions
Data Source
AI summary
A semiconductor device includes a first and a second semiconductor fins extending along a first direction; an isolation region disposed between respective lower portions of the first and second semiconductor fins; a dielectric structure disposed between the first and the second semiconductor fins and above the isolation region, with a bottom surface aligned with a top surface of the isolation region; a gate isolation structure vertically disposed above the dielectric structure; and a metal gate layer extending along a second direction perpendicular to the first direction. The metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure separates the first and second portions of the metal gate layer from each other and includes a top portion vertically extending above the dielectric structure and a bottom portion extending into the dielectric structure. A width of the top portion of the gate isolation is greater than a width of the dielectric structure.