FinFET Cut Metal Gate Isolation for Low Capacitance and Etch Robustness
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing capacitance and preventing metal extrusion issues in cut metal gate (CMG) trenches filled with low-k dielectric materials, which are prone to damage during etching processes, leading to increased complexity and performance degradation in high-k metal gate (HKMG) approaches.
Innovation Solution
A semiconductor structure and method involving the use of a low-k dielectric material in CMG trenches, where a nitrogen-containing treatment and curing process convert the low-k material into a solid dielectric feature with a higher nitrogen concentration, and a dielectric layer with different materials and thicknesses are used to reduce capacitance and mitigate metal extrusion, while maintaining performance by forming a cut metal gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If low-k dielectric material is used in CMG trenches, then capacitance is reduced, but the material is damaged during etching processes
Solution Approach 1:
A nitrogen-containing dielectric layer is formed over the low-k dielectric material before the etching process. This preliminary protective layer prevents damage to the low-k material during subsequent etching operations, allowing the capacitance-reducing low-k material to be used effectively in CMG trenches
Solution Approach 2:
The nitrogen-containing dielectric layer acts as an intermediary protective barrier between the etching process and the low-k dielectric material. This intermediate layer withstands the etching conditions while protecting the underlying low-k material, enabling both low capacitance and material integrity
2Reliability
If high-k dielectric material is used to reduce gate leakage, then device performance is improved, but the approach becomes complicated with metal extrusion issues
Solution Approach 1:
The patent uses a sacrificial high-k dielectric layer that is temporarily present during fabrication to control gate leakage, but is subsequently removed. This disposable approach allows high-k material benefits to be achieved without the long-term complexity and metal extrusion issues associated with permanent high-k dielectric structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance and prevents metal extrusion, enhancing the reliability and efficiency of the semiconductor structure by using a low-k dielectric material that withstands etching and maintains performance, addressing the complexity and issues associated with high-k dielectric materials.
Implementation Method 1
a nitrogen-containing treatment and curing process convert the low-k material into a solid dielectric feature with a higher nitrogen concentration
Data Source
AI summary
A semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.