FinFET Gate Isolation Structure for Dense, Reliable Patterning
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates finer patterns and integration densities, which pose challenges in overcoming limitations due to reduced planar MOSFET sizes, particularly in developing FinFETs with improved reliability and mass productivity.
Innovation Solution
A semiconductor device design featuring a substrate with distinct active regions, gate electrodes, and a gate isolation layer with stacked conductive layers, ensuring electrical isolation and enhanced structural integrity through specific contact points and materials, facilitating the formation of multi-bridge channel FETs and gate-all-around transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar MOSFET size is reduced to achieve higher integration density, then integration density is improved, but reliability deteriorates due to limitations in operating properties
Solution Approach 1:
The patent transitions from planar MOSFET to FinFET structure, utilizing three-dimensional channel architecture. The gate electrode wraps around the channel in a FinFET configuration, providing better gate control over the channel current and improving device reliability while maintaining high integration density through vertical channel formation.
Solution Approach 2:
The patent employs multi-layer gate electrode structures with different conductive materials (e.g., polysilicon, metal layers) to optimize both electrical performance and mechanical stability. This composite approach allows fine-tuning of device characteristics to maintain reliability at scaled dimensions.
2Productivity
If pattern width and spacing are reduced to achieve finer patterns, then integration density is improved, but manufacturing precision deteriorates
Solution Approach 1:
The gate electrode is divided into multiple conductive layers that can be formed and patterned separately using different manufacturing processes. This segmentation allows each layer to be optimized for its specific function, with intermediate layers providing structural support that eases the manufacturing precision requirements for the overall fine-pitch structure.
Solution Approach 2:
By forming vertical fins and three-dimensional channel structures, the patent reduces the lateral pattern dimensions while maintaining manufacturable feature sizes through vertical dimension exploitation. The gate-all-around structure wraps around the channel, providing control without requiring proportionally smaller lateral features.
3Ease of manufacture
If gate electrode structure is simplified to improve ease of manufacture, then ease of manufacture is improved, but electrical isolation deteriorates
Solution Approach 1:
The gate electrode is segmented into multiple conductive layers with distinct functions. Intermediate insulating layers are maintained between certain conductive layers to provide electrical isolation where needed, while allowing continuous coverage for gate control. This segmented approach maintains manufacturing simplicity through standardized layer formation processes.
Solution Approach 2:
Intermediate insulating layers serve as mediators between conductive gate layers, providing necessary electrical isolation while allowing the overall gate structure to maintain simple fabrication processes. These intermediary layers enable independent formation and patterning of conductive layers without compromising isolation.
Data Source
AI summary
A semiconductor device includes a first active region and a second active region on a substrate and spaced apart from each other; a first gate electrode crossing the first active region; a second gate electrode crossing the second active region; and a gate isolation layer between the first and second gate electrodes, wherein the second gate electrode includes a first conductive layer and a second conductive layer stacked in order, the first gate electrode includes the second conductive layer and is spaced apart from the first conductive layer, a first side surface of the gate isolation layer faces the first gate electrode and is in contact with the second conductive layer, and a second side surface of the gate isolation layer faces the second gate electrode and is in contact with the first conductive layer and the second conductive layer in order from a lower portion.