FinFET Gate Structure Segmentation to Reduce Junction Leakage
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Solution Overview
Problem
Conventional fin field effect transistors (Fin FETs) face performance issues due to incomplete removal of gate structure materials at junctions between the gate and fins, leading to leakage currents caused by remaining gate structure materials connecting with source-drain doped regions.
Innovation Solution
A fabrication method involving a first etching process on the sidewalls of an initial gate structure to form a gate structure with distinct regions, where the first region is smaller in size and located at the bottom of the second region, preventing connection with source-drain doped regions and reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a multi-step etching process is used to form the gate structure, then the gate structure can be formed on the fins, but the gate structure materials cannot be completely removed at the junctions due to limited space, resulting in remaining materials that cause leakage currents
Solution Approach 1:
The gate structure is divided into two distinct regions: a first region with a larger size in the extending direction of the fins, and a second region with a smaller size. This segmentation allows the etching process to effectively remove gate structure materials at the junctions in the first region while maintaining the necessary gate structure in the second region, thereby preventing leakage currents without compromising the overall gate structure formation.
Solution Approach 2:
Different regions of the gate structure are given different sizes and configurations tailored to their specific functional requirements. The first region has a larger dimension to ensure complete removal of gate materials at junctions, while the second region has a smaller dimension to maintain proper gate structure. This local differentiation resolves the contradiction by optimizing each region for its specific purpose.
2Object-affected harmful factors
If the gate structure size is reduced to remove remaining materials at junctions, then leakage currents are reduced, but the gate structure may become too small to effectively control the channel current
Solution Approach 1:
The gate structure is segmented into two regions with different dimensions. The first region has a larger size that maintains adequate channel current control capability, while the second region has a smaller size that facilitates complete removal of gate structure materials at junctions. This segmentation allows both requirements to be satisfied simultaneously: the first region ensures reliable channel control, while the second region prevents leakage currents.
Solution Approach 2:
Different regions of the gate structure are assigned different sizes according to their specific functional needs. The first region maintains a larger dimension for effective channel current control, while the second region adopts a smaller dimension to eliminate leakage paths. This local quality differentiation resolves the contradiction between channel control reliability and leakage prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves semiconductor device performance by minimizing leakage currents and enhancing the gate structure's dimensions, ensuring better isolation and reduced leakage, thus improving overall device performance.
Implementation Method 1
performing a first etching process on sidewalls of the initial gate structure to form a gate structure
Data Source
AI summary
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, having a plurality of fins on a surface of the substrate; a gate structure across the plurality of fins. The gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins. The gate structure includes a first region and a second region on the first region. A bottom boundary of the second region is higher than the top surface of the plurality of fins. A size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.