FinFET Gate Layer Uniformity via Multi-Layer CMP
Solution Overview
Problem
Poor gate height control and uniformity in FinFET fabrication processes pose a challenge, particularly during the replacement metal gate stage, which can affect device performance and increase the risk of dummy gate removal.
Innovation Solution
A method involving the formation of two material layers with a stop layer, where different polishing selectivities are used in a chemical mechanical polishing process to control and uniformize the gate layer height, allowing for precise removal of the top material and stop layers to form a gate layer with improved uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional single-layer gate formation is used, then the fabrication process is simple, but gate height uniformity is poor
Solution Approach 1:
The gate layer is divided into multiple material layers (first material layer, second material layer, third material layer) with different thicknesses and polishing rates. This segmentation allows selective removal of excess material through CMP to achieve uniform gate height while maintaining process simplicity.
Solution Approach 2:
Different material layers are selected with different polishing rates to control the gate height. The first material layer has a first polishing rate, the second material layer has a second polishing rate, and the third material layer has a third polishing rate, allowing precise control of gate height uniformity through parameter optimization.
2Productivity
If gate height is increased to improve device performance, then current increases, but gate height control becomes more difficult
Solution Approach 1:
The gate structure uses multiple material layers with different polishing characteristics that can be dynamically adjusted during CMP processing. This allows the gate height to be optimized for current performance while maintaining precise control through the differential polishing rates of each layer.
Solution Approach 2:
By changing the polishing rates of different material layers (first, second, and third polishing rates), the gate height can be optimized to increase device current while maintaining precise control over the final gate height uniformity.
3Adaptability or versatility
If dummy gate is removed during RMG stage, then metal gate functionality is achieved, but process complexity increases
Solution Approach 1:
The gate structure is preliminarily formed with multiple material layers that are designed to be selectively removed during the RMG stage. The first, second, and third material layers are prepared in advance with specific polishing rates to facilitate subsequent dummy gate removal and metal gate formation, achieving adaptability while managing process complexity.
4Shape
If CMP is used to planarize the gate layer, then surface flatness is improved, but material removal control becomes critical
Solution Approach 1:
The gate layer is segmented into multiple material layers with different polishing rates. During CMP, each layer removes at a different rate (first, second, and third polishing rates), which provides inherent control over material removal and achieves surface flatness while managing the criticality of removal control.
Solution Approach 2:
By utilizing material layers with different polishing rates, the CMP process can control material removal more precisely. The differential polishing rates allow the process to achieve surface flatness while the parameter variations provide built-in control mechanisms to manage material removal criticality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances gate layer uniformity and control, thereby improving the overall performance and reliability of FinFET devices by ensuring consistent gate height and reducing the risk of defects during the RMG stage.
Implementation Method 1
performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer
Data Source
AI summary
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.