FinFET Gate Structure With Variable Conductive-Layer Thickness
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multi-functional semiconductor devices necessitates the development of semiconductor devices with fine patterns and three-dimensional channels to overcome the limitations of planar MOSFETs, requiring improved electrical characteristics and reliability.
Innovation Solution
A semiconductor device design featuring a substrate with active fins and channel layers, intersected by gate patterns with specific conductive and dielectric layers, including a conductive liner and inner portions with varying thicknesses to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to meet high performance demand, then productivity and functionality are improved, but manufacturing precision and reliability deteriorate due to fine pattern requirements
Solution Approach 1:
The patent transitions from planar MOSFETs to FinFETs with three-dimensional channels, adding a vertical dimension to the channel structure. This enables continued scaling and integration while maintaining manufacturability, as the vertical channel provides additional conduction path without requiring proportionally smaller lateral dimensions.
Solution Approach 2:
The gate pattern is divided into multiple conductive layers (first conductive layer, second conductive layer) separated by gate dielectric layers. This segmentation allows for better control of the gate structure during fabrication and enables independent optimization of different gate regions, improving manufacturing precision for fine patterns.
2Productivity
If planar MOSFET size is reduced to increase integration, then productivity is improved, but electrical characteristics deteriorate due to size limitations
Solution Approach 1:
The invention adopts FinFET architecture with vertical channels instead of planar horizontal channels. This three-dimensional structure provides enhanced electrical characteristics including better gate control and higher drive current density, allowing integration density to increase without sacrificing electrical performance.
Solution Approach 2:
The gate pattern uses composite structure with multiple conductive layers and gate dielectric layers. This composite approach enables optimization of electrical characteristics through material selection and layer configuration, maintaining reliability while enabling size reduction for higher integration.
3Productivity
If fine patterns are implemented to increase integration, then productivity is improved, but device complexity increases making manufacturing more difficult
Solution Approach 1:
The gate structure is segmented into multiple conductive layers and gate dielectric layers. This segmentation simplifies the manufacturing process by allowing each layer to be formed and patterned separately using standard semiconductor fabrication techniques, reducing the complexity of creating fine patterns compared to attempting to form the entire gate structure in a single step.
Solution Approach 2:
The gate dielectric layers are formed between the conductive layers in advance, creating a pre-configured multi-layer gate structure. This preliminary action simplifies subsequent processing steps and enables better control over the final gate pattern dimensions, reducing manufacturing complexity for fine integrated structures.
Data Source
AI summary
A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.