FinFET Gate Structure for Leakage Reduction
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Solution Overview
Problem
As semiconductor devices shrink, the short channel leakage effect leads to inadequate gate control over the channel region, resulting in increased leakage current, particularly in conventional planar transistors, and variations in footing or notching features at the gate bottom cause electrical shorts and non-uniform breakdown voltage across devices.
Innovation Solution
A FinFET structure with a gate that wraps around the active region, featuring a lower width near the isolation layer and a wider upper width, manufactured using a method that includes spatial etching gas mode changes and epitaxial growth to achieve uniform notching, reducing electrical shorts and enhancing control over the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used with reduced feature size to increase integration density, then more components can be integrated into a given area, but leakage current increases due to short channel leakage effect
Solution Approach 1:
The patent transitions from conventional planar transistors to FinFET structures, adding a vertical dimension to the channel. The active region protrudes upward from the substrate surface, creating a three-dimensional fin structure that allows the gate to control the channel from multiple sides (top and two sidewalls), thereby significantly reducing short channel leakage effect while maintaining scaled dimensions
Solution Approach 2:
The gate structure in the FinFET wraps around the active region in a curved configuration, surrounding three sides of the rectangular fin structure. This curved gate geometry provides enhanced electrostatic control over the channel region compared to a planar gate, effectively suppressing leakage current at scaled dimensions
2Reliability
If the gate structure wraps around the active region to reduce leakage current, then control over the channel is improved, but manufacturing complexity increases due to notching and epitaxial growth processes
Solution Approach 1:
The patent employs preliminary actions in the manufacturing process by first forming mandrels and isolation layers before creating the fin structures. The notching process is performed as a preliminary step to define the gate footprint, and epitaxial growth is used early to form the active region, simplifying subsequent processing steps
Solution Approach 2:
The manufacturing process is divided into distinct segmented steps: forming isolation layers, creating mandrels, performing notching, executing epitaxial growth for fin formation, and finally creating the wrapped gate structure. This segmentation allows each complex operation to be optimized independently while maintaining overall process control
3Productivity
If feature size is reduced to increase integration density, then more components fit in a given area, but gate control over the channel region becomes inadequate, especially far from the gate
Solution Approach 1:
By transitioning to a vertical fin structure, the gate gains control over the channel from three sides (top and two sidewalls) rather than just one side as in planar devices. This multi-sided control extends the effective gate influence to regions farther from the gate, maintaining reliable control even as horizontal dimensions are scaled down
Solution Approach 2:
The FinFET structure employs composite material arrangements with the active region protruding vertically from the substrate, surrounded by a wrapped gate structure. This composite geometry creates enhanced electrostatic control that maintains effective gate influence over the entire channel length, including regions distant from the gate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FinFET structure effectively reduces leakage current and achieves better within-wafer device uniformity by ensuring consistent notching features, improving breakdown voltage consistency and device performance.
Implementation Method 1
manufactured using a method that includes spatial etching gas mode changes
Implementation Method 2
manufactured using a method that includes spatial etching gas mode changes and epitaxial growth
Data Source
AI summary
Present disclosure provides a semiconductor structure, including a substrate having a center portion and an edge portion, an isolation layer over the substrate; a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer, a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at an edge portion of the substrate, and a second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at a center portion of the substrate. A lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin.